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1. KR1020000070994 - SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS USING THE SEMICONDUCTOR DEVICE

Office
Republic of Korea
Application Number 1019997007260
Application Date 11.08.1999
Publication Number 1020000070994
Publication Date 25.11.2000
Publication Kind A
IPC
G11C 11/404
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
403with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
404with one charge-transfer gate, e.g. MOS transistor, per cell
CPC
G11C 11/4074
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
4074Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
Applicants SEIKO EPSON CORPORATION
야스카와 히데아키세이코 엡슨 가부시키가이샤
Inventors MARUYAMA AKIRA
마루야마아키라
Agents 이병호
Priority Data 97-341088 11.12.1997 JP
Title
(EN) SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS USING THE SEMICONDUCTOR DEVICE
(KO) 반도체 기억장치, 반도체 장치 및 그것을 사용한 전자기기
Abstract
(EN)

A memory cell (1) is provided with a MOS transistor (5) and a data holding capacitor (7). One of the two input-output electrodes of the transistor (5) is connected to a bit line (36) and the gate electrode of the transistor (5) is connected to a word line (37). The first electrode (6) of the capacitor (7) is connected to the other input-output electrode of the transistor (5), and the second electrode (14) is connected to a potential control circuit (40). When the data held in the memory cell (5) is HIGH, the potential control circuit (40) changes the potential at the second electrode (14) to a ground potential GND from a precharge potential VCC/2 after the write/read of the data held in the memory cell (1). When the data held in the memory cell (5) is LOW, the circuit (40) changes the potential at the second electrode (14) to a power supply potential VCC from the precharge potential VCC/2 after the write/read of the data.

© KIPO & WIPO 2007


(KO) 메모리 셀(1)은, MOS 트랜지스터(5)와 데이터 유지용량(7)을 갖는다. M0S 트랜지스터(5)의 2개의 입출력 전극의 한쪽은 비트라인(36)과 접속되며, 게이트 전극이 워드라인(37)에 접속된다. 데이터 유지용량(7)의 제1 전극(6)은 MOS 트랜지스터(5)의 다른쪽의 입출력 전극에 접속되고, 제2 전극(14)은 전위제어회로(40)에 접속된다. 전위제어어 회로(40)는, 메모리 셀(5)에 유지되는 데이터가 HIGH일 때에는, 그 데이터의 기입 및 판독 동작의 종료후에, 데이터 유지용량(7)의 제2 전극(14)의 전위를, 프리차지 전위(VCC/2)로부터 접지 전위(GND)로 변경제어한다. 전위제어 회로(40)는, 메모리 셀(5)에 유지되는 데이터가 LOW일 때에는, 그 데이터의 기입 및 판독 동작의 종료후에, 데이터 유지용량(7)의 제2 전극(14)의 전위를, 프리차지 전위(VCC/2)로부터 전원전위(VCC)로 변경 제어한다.
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