KR1020170012462 3차원 메모리 디바이스의 동적 워드 라인 기반 구성을 위한 방법 및 시스템

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Republic of Korea

Application Number 1020167036803

Application Date 14.05.2015

Publication Number 1020170012462

Publication Date 02.02.2017

Grant Number 101995624

Grant Date 02.07.2019

Publication Kind B1

IPC

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Applicants 샌디스크 테크놀로지스 엘엘씨

Inventors 히긴스, 제임스, 엠.
엘리스, 로버트, 더블유.
다라, 네일, 알.
올브리치, 아론, 케이.
칸카니, 나브니스
스프라우스, 스티븐

Agents 양영준
정은진
백만기

Priority Data 14298841 06.06.2014 US
62/005,930 30.05.2014 US

Title

(KO) 3차원 메모리 디바이스의 동적 워드 라인 기반 구성을 위한 방법 및 시스템

Abstract

(KO) 메모리 제어기는 3D 메모리 디바이스의 각자의 블록과 연관된 복수의 워드 라인들을 제1 구성으로 구성하고 - 여기서 제1 구성은 3D 메모리 디바이스의 기판에 대한 각각의 워드 라인의 수직 위치들에서 적어도 부분적으로 결정된 복수의 워드 라인들의 각각의 워드 라인에 대한 구성 파라미터 세트를 포함함 -, 복수의 워드 라인들이 제1 구성으로 구성되어 있는 동안, 각자의 블록에 데이터를 쓰고 각자의 블록으로부터 데이터를 읽는다. 각자의 블록에 대해, 메모리 제어기는, 각자의 워드 라인에 관한 제1 트리거 조건을 검출한 것에 응답하여, 복수의 워드 라인들의 각자의 워드 라인에 대응하는 각자의 구성 파라미터 세트 내의 제1 파라미터를 조절하고, 제1 파라미터를 조절한 후에, 각자의 워드 라인에 데이터를 쓰고 각자의 워드 라인으로부터 데이터를 읽는다.

G	PHYSICS
11	INFORMATION STORAGE
C	STATIC STORES
16	Erasable programmable read-only memories
02	electrically programmable
06	Auxiliary circuits, e.g. for writing into memory
34	Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

G	PHYSICS
06	COMPUTING; CALCULATING OR COUNTING
F	ELECTRIC DIGITAL DATA PROCESSING
11	Error detection; Error correction; Monitoring
07	Responding to the occurrence of a fault, e.g. fault tolerance
08	Error detection or correction by redundancy in data representation, e.g. by using checking codes
10	Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens

G	PHYSICS
11	INFORMATION STORAGE
C	STATIC STORES
16	Erasable programmable read-only memories
02	electrically programmable
04	using variable threshold transistors, e.g. FAMOS

G	PHYSICS
11	INFORMATION STORAGE
C	STATIC STORES
16	Erasable programmable read-only memories
02	electrically programmable
06	Auxiliary circuits, e.g. for writing into memory
10	Programming or data input circuits

G	PHYSICS
11	INFORMATION STORAGE
C	STATIC STORES
29	Checking stores for correct operation; Testing stores during standby or offline operation
02	Detection or location of defective auxiliary circuits, e.g. defective refresh counters

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1. KR1020170012462 - 3차원 메모리 디바이스의 동적 워드 라인 기반 구성을 위한 방법 및 시스템

H	ELECTRICITY
01	BASIC ELECTRIC ELEMENTS
L	SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27	Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02	including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04	the substrate being a semiconductor body
10	including a plurality of individual components in a repetitive configuration
105	including field-effect components
112	Read-only memory structures
115	Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563	with charge-trapping gate insulators, e.g. MNOS or NROM
11578	characterised by three-dimensional arrangements, e.g. with cells on different height levels
1158	with source and drain on different levels, e.g. with sloping channels
11582	the channels comprising vertical portions, e.g. U-shaped channels

G	PHYSICS
06	COMPUTING; CALCULATING; COUNTING
F	ELECTRIC DIGITAL DATA PROCESSING
11	Error detection; Error correction; Monitoring
07	Responding to the occurrence of a fault, e.g. fault tolerance
08	Error detection or correction by redundancy in data representation, e.g. by using checking codes
10	Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1008	in individual solid state devices
1072	in multilevel memories

G	PHYSICS
11	INFORMATION STORAGE
C	STATIC STORES
8	Arrangements for selecting an address in a digital store
08	Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

G	PHYSICS
11	INFORMATION STORAGE
C	STATIC STORES
29	Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04	Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08	Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12	Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
38	Response verification devices
42	using error correcting codes [ECC] or parity check

G	PHYSICS
11	INFORMATION STORAGE
C	STATIC STORES
8	Arrangements for selecting an address in a digital store
08	Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines