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1. KR1020170012462 - 3차원 메모리 디바이스의 동적 워드 라인 기반 구성을 위한 방법 및 시스템

Office
Republic of Korea
Application Number 1020167036803
Application Date 14.05.2015
Publication Number 1020170012462
Publication Date 02.02.2017
Grant Number 101995624
Grant Date 02.07.2019
Publication Kind B1
IPC
G11C 16/34
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G06F 11/10
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G11C 16/04
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
04using variable threshold transistors, e.g. FAMOS
G11C 16/10
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
10Programming or data input circuits
G11C 29/02
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G11C 29/42
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
04Detection or location of defective memory elements
08Functional testing, e.g. testing during refresh, power-on self testing or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing
38Response verification devices
42using error correcting codes or parity check
CPC
G11C 16/3404
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
3404Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
G06F 11/1072
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1008in individual solid state devices
1072in multilevel memories
G11C 16/0483
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
04using variable threshold transistors, e.g. FAMOS
0483comprising cells having several storage transistors connected in series
G11C 16/10
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
10Programming or data input circuits
G11C 16/349
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
349Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
G11C 29/025
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
025in signal lines
Applicants 샌디스크 테크놀로지스 엘엘씨
Inventors 히긴스, 제임스, 엠.
엘리스, 로버트, 더블유.
다라, 네일, 알.
올브리치, 아론, 케이.
칸카니, 나브니스
스프라우스, 스티븐
Agents 양영준
정은진
백만기
Priority Data 14298841 06.06.2014 US
62/005,930 30.05.2014 US
Title
(KO) 3차원 메모리 디바이스의 동적 워드 라인 기반 구성을 위한 방법 및 시스템
Abstract
(KO) 메모리 제어기는 3D 메모리 디바이스의 각자의 블록과 연관된 복수의 워드 라인들을 제1 구성으로 구성하고 - 여기서 제1 구성은 3D 메모리 디바이스의 기판에 대한 각각의 워드 라인의 수직 위치들에서 적어도 부분적으로 결정된 복수의 워드 라인들의 각각의 워드 라인에 대한 구성 파라미터 세트를 포함함 -, 복수의 워드 라인들이 제1 구성으로 구성되어 있는 동안, 각자의 블록에 데이터를 쓰고 각자의 블록으로부터 데이터를 읽는다. 각자의 블록에 대해, 메모리 제어기는, 각자의 워드 라인에 관한 제1 트리거 조건을 검출한 것에 응답하여, 복수의 워드 라인들의 각자의 워드 라인에 대응하는 각자의 구성 파라미터 세트 내의 제1 파라미터를 조절하고, 제1 파라미터를 조절한 후에, 각자의 워드 라인에 데이터를 쓰고 각자의 워드 라인으로부터 데이터를 읽는다.