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1. JP2020187659 - INFORMATION PROCESSING APPARATUS

Office
Japan
Application Number 2019093182
Application Date 16.05.2019
Publication Number 2020187659
Publication Date 19.11.2020
Publication Kind A
IPC
G06F 12/00
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
G06F 13/38
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
CPC
G06F 13/1605
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
1605based on arbitration
G06F 13/372
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
36for access to common bus or bus system
368with decentralised access control
372using a time-dependent priority, e.g. individually loaded time counters or time slot
G06F 13/1668
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
1668Details of memory controller
G06F 13/4282
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
42Bus transfer protocol, e.g. handshake; Synchronisation
4282on a serial bus, e.g. I2C bus, SPI bus
Applicants OMRON CORP
オムロン株式会社
Inventors TAMAI TOSHINORI
玉井 俊規
Agents 村上 尚
Title
(EN) INFORMATION PROCESSING APPARATUS
(JA) 情報処理装置
Abstract
(EN)

PROBLEM TO BE SOLVED: To prevent the occurrence of memory contention without causing an operation unit of a control device to execute arbitration processing for preventing memory contention.

SOLUTION: In a period (T3) from a time (t5) at which a transmission time (T2) of minimum payload data (D6) is determined to exceed a reference value in a control period (C2) until a time (t6) at which a communication interface (42) transmits minimum payload data (D8) transmitted subsequent to the latest minimum payload data (D7) that has been transmitted at the time (t5), a unit (20) causes the communication interface (42) to wait for the transmission of the minimum payload data (D8).

SELECTED DRAWING: Figure 2

COPYRIGHT: (C)2021,JPO&INPIT


(JA)

【課題】メモリ競合を防止するための調停処理を制御装置の演算部に実行させることなく、メモリ競合の発生を抑制する。
【解決手段】制御周期(C2)において最小ペイロードデータ(D6)の送信時間(T2)が基準値を超えると判定された時刻(t5)から、時刻(t5)において送信済みの直近の最小ペイロードデータ(D7)の次に送信される最小ペイロードデータ(D8)を通信インタフェース(42)が送信する時刻(t6)までの期間(T3)において、通信インタフェース(42)に最小ペイロードデータ(D8)の送信を待機させるユニット(20)。
【選択図】図2