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1. JP2017510075 - 半導体パッケージにおけるはんだボール接続でのフェースアップ基板集積化

Office
Japan
Application Number 2016557253
Application Date 11.03.2015
Publication Number 2017510075
Publication Date 06.04.2017
Publication Kind A5
IPC
H01L 23/12
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
12Mountings, e.g. non-detachable insulating substrates
H01L 23/15
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
12Mountings, e.g. non-detachable insulating substrates
14characterised by the material or its electrical properties
15Ceramic or glass substrates
H05K 1/14
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
02Details
14Structural association of two or more printed circuits
H05K 3/36
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
36Assembling printed circuits with other printed circuits
CPC
H01L 23/48
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; ; Selection of materials therefor
H01L 23/5385
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
538the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
5385Assembly of a plurality of insulating substrates
H01L 23/645
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
58Structural electrical arrangements for semiconductor devices not otherwise provided for ; , e.g. in combination with batteries
64Impedance arrangements
645Inductive arrangements
H01L 2924/00
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
H01L 2924/0002
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
0001Technical content checked by a classifier
0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
H01L 2924/19101
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
191Disposition
19101of discrete passive components
Applicants クアルコム,インコーポレイテッド
Inventors デイク・ダニエル・キム
ジョンヘ・キム
チェンジエ・ズオ
チャンハン・ホビー・ユン
マリオ・フランシスコ・ヴェレス
ロバート・ポール・ミクルカ
Agents 村山 靖彦
黒田 晋平
Priority Data 14220913 20.03.2014 US
Title
(JA) 半導体パッケージにおけるはんだボール接続でのフェースアップ基板集積化
Abstract
(JA)

システムおよび方法は、受動構成要素および第1の組の1つまたは複数のパッケージパッドがガラス基板の面上に形成される、第1の基板または2Dパッシブオンガラス(POG)構造を備える半導体パッケージに関する。半導体パッケージは、第2の組の1つまたは複数のパッケージパッドが第2の基板または積層基板の面上に形成される第2の基板または積層基板をやはり含む。はんだボールは、第1の組の1つまたは複数のパッケージパッドを第2の組の1つまたは複数のパッケージパッドと接触させるように落とされて構成され、第1の基板または2D POG構造は、第2の基板または積層基板の面上にフェースアップで配置される。プリント回路板(PCB)を、第2の基板または積層基板の底側に結合することができる。


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