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1. JP2014146728 - LOWER RECEIVING PINS ARRANGEMENT DETERMINATION SUPPORT DEVICE AND ARRANGEMENT DETERMINATION SUPPORT METHOD

Office
Japan
Application Number 2013015079
Application Date 30.01.2013
Publication Number 2014146728
Publication Date 14.08.2014
Grant Number 5903588
Grant Date 25.03.2016
Publication Kind B2
IPC
H05K 13/04
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
13Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
04Mounting of components
Applicants PANASONIC CORP
パナソニックIPマネジメント株式会社
Inventors TAKEHARA YUKI
竹原 裕起
YOKOI TAKAAKI
横井 敬明
Agents 藤井 兼太郎
鎌田 健司
前田 浩夫
Title
(EN) LOWER RECEIVING PINS ARRANGEMENT DETERMINATION SUPPORT DEVICE AND ARRANGEMENT DETERMINATION SUPPORT METHOD
(JA) 下受けピンの配置決定支援装置および配置決定支援方法
Abstract
(EN)

PROBLEM TO BE SOLVED: To provide an arrangement determination support device and an arrangement determination support method of lower receiving pins used for lower receiving pins arrangement determination process handling a high density packaging substrate, which is capable of precisely detecting an interference occurrence between a lower receiving pin and an existing mounted component.

SOLUTION: In a process to determining a disposition of a lower receiving pin module 22 in a substrate holder unit receiving a component mounted plane of a substrate 3 from lower surface side, the arrangement determination support method includes the steps of: displaying an image including a substrate image representing a shape and disposition of an existing mounted component on the mounted plane; inputting a disposition position of the lower receiving pin module 22 on the displayed image; displaying a synthetic image in which a substrate image is overlapped with a pin disposition image inputted the disposition position; and adding an image of a head 25 of a shaft 24 and an image of a contact part 25a which comes into contact with the lower surface of the substrate 3 to support the same to a plane image of the lower receiving pin module 22 in the pin disposition image; to thereby determine an interference occurrence between a lower receiving pin and an existing mounted component.

COPYRIGHT: (C)2014,JPO&INPIT


(JA)

【課題】高実装密度の基板を対象とする下受けピンの配置決定作業において、下受けピンと既実装部品との干渉発生の有無をより精緻に判断することができる下受けピンの配置決定支援装置および配置決定支援方法を提供する。
【解決手段】基板保持部において基板3の既実装面を下面側から下受けする下受けピンモジュール22の配置の決定に際し、既実装面における既実装部品の形状・配置を示す基板画像を含む画像を表示させ、表示された画像上に下受けピンモジュール22の配置位置を入力し、配置位置が入力されたピン配置画像を基板画像に重ねた合成画像を表示させ、さらにピン配置画像における下受けピンモジュール22の平面画像に軸部24の頂部25の画像と基板3の下面に当接して下受けする当接部25aの画像とを含ませ、下受けピンと既実装部品との干渉発生の有無を判断する。
【選択図】図9