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1. IN201627027789 - FACE UP SUBSTRATE INTEGRATION WITH SOLDER BALL CONNECTION IN SEMICONDUCTOR PACKAGE

Office
India
Application Number 201627027789
Application Date 16.08.2016
Publication Number 201627027789
Publication Date 07.10.2016
Publication Kind A
IPC
H05K 1/02
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
02Details
H05K 1/14
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
02Details
14Structural association of two or more printed circuits
H05K 3/36
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
36Assembling printed circuits with other printed circuits
Applicants QUALCOMM INCORPORATED
Inventors KIM Daeik Daniel
KIM Jonghae
ZUO Chengjie
YUN Changhan Hobie
VELEZ Mario Francisco
MIKULKA Robert Paul
Priority Data 14220913 20.03.2014 US
Title
(EN) FACE UP SUBSTRATE INTEGRATION WITH SOLDER BALL CONNECTION IN SEMICONDUCTOR PACKAGE
Abstract
(EN) FACE UP SUBSTRATE INTEGRATION WITH SOLDER BALL CONNECTION IN SEMICONDUCTOR PACKAGE Systems and methods relate to a semiconductor package 200 comprising a first substrate or a 2D passive on glass (POG) structure with a passive component 204 and a first set of one or more package pads 203 formed on a face of a glass substrate 202. The semiconductor package also includes a second or laminate substrate 207 with a second set of one or more package pads 205 formed on a face of the second or laminate substrate. Solder balls 206 are dropped configured to contact the first set of one or more package pads with the second set of one or more package pads wherein the first substrate or the 2D POG structure is placed face up on the face of the second or laminate substrate. A printed circuit board (PCB) 208 can be coupled to a bottom side of the second or laminate substrate.
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BR112016021591This application is not viewable in PATENTSCOPE because the national phase entry has not been published yet or the national entry is issued from a country that does not share data with WIPO or there is a formatting issue or an unavailability of the application.