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1. GB2560159 - Widening arithmetic in a data processing apparatus

Office
United Kingdom
Application Number 201702918
Application Date 23.02.2017
Publication Number 2560159
Publication Date 05.09.2018
Publication Kind B
IPC
G06F 9/30
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
CPC
G06F 9/3001
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
30007to perform operations on data operands
3001Arithmetic instructions
G06F 9/30036
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
30007to perform operations on data operands
30036Instructions to perform operations on packed data, e.g. vector operations
G06F 9/30109
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30098Register arrangements
30105Register structure
30109having multiple operands in a single register
G06F 9/30014
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
30007to perform operations on data operands
3001Arithmetic instructions
30014with variable precision
G06F 17/16
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
17Digital computing or data processing equipment or methods, specially adapted for specific functions
10Complex mathematical operations
16Matrix or vector computation ; , e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
G06F 9/3885
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3885using a plurality of independent parallel functional units
Applicants ADVANCED RISC MACH LTD
Inventors DAVID HENNAH MANSELL
Priority Data 201702918 23.02.2017 GB
Title
(EN) Widening arithmetic in a data processing apparatus
Abstract
(EN) A data processing apparatus comprises decoder circuitry responsive to an instruction (320 in Figure 9B) specifying a first source register and a second source register. In response to the instruction, processing circuitry performs a dot product operation, in which at least a first data element and a second data element are extracted from each of the first source register and the second source register, then at least first data element pairs and second data element pairs are multiplied together 340-346, with the results summed 348. The dot product operation is performed independently in each of multiple intra-register lanes across each of the first source register and the second source register, treating each as a vector. A widening operation with a large density of operations per instruction may thus be provided. FMA (fused multiply-add) units (514-520 in Figure 15A), and a dot-product and accumulate operation (Figure 14), may be implemented.