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1. (EP2467984) WIRELESS RECEIVER
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Claims

1. A receiver (1) operable according to a standard to decode digital data from an analog signal, comprising an analog front-end (50) and a digital decoder (52), wherein the analog front-end (50) comprises a plurality of analog components including an analog signal input for receiving the analog signal, at least one amplifier (2) arranged to amplify the analog signal, and an analog-to-digital converter -ADC- (18) arranged to convert the amplified analog signal into a digital signal, and wherein the digital decoder (52) comprises a digital signal input connected to the output of the ADC and a demodulator (26) comprising a plurality of digital components connected to be driven by a clock signal having a chip frequency, wherein the chip frequency corresponds to the frequency of the bits in the received signal, the digital components (52) including:

a sampler (70) operable to sample the digital signal at a sampling frequency which is a multiple of the chip frequency;

a correlation unit (72) operable to process a set of bits, referred to as a chip-code, in the sampled digitised signal using a double correlation function and output therefrom a set of correlation values, wherein the set of correlation values is an indicator of likely mapping between the chip-code that has been processed and a set of possible chip-codes defined according to the standard, wherein the double correlation function is performed over two dimensions comprising a number of bits per chip-code and a lag delay of the set of bits;

a symbol selection unit (76) having the function of deciding which chip-code, referred to as a symbol, has been received based on an analysis of each set of correlation values; and

a frequency correction unit (84) operable to output a frequency control signal for momentary adjustment of the chip frequency dependent upon the correlation values output from the correlation unit (72) by increasing or decreasing the chip frequency for an amount of time based on a measurement of whether the maximum correlation value among each set of correlation values occurs earlier or later than predicted according to the chip frequency currently in use.


  2. The receiver of claim 1, further comprising a synchronisation unit having an input connected to receive the frequency control signal from the frequency correction unit, and an output operable to output a clock signal at the chip frequency to the components of the demodulator, wherein the synchronisation unit sets the chip frequency having regard to the frequency control signal.
  3. The receiver of claim 1 or 3, wherein the digital decoder further comprises:

an averaging unit interposed between the correlation unit and the symbol selection unit, the averaging unit being operable to modify the correlation values output by the correlation unit by averaging each correlation value over a succession of time intervals spanning a timing window centred around a predicted correct detection time.


  4. The receiver of claim 1, 2 or 3, further comprising a signal quality analysis unit comprising:

an input connected to receive an analog received signal strength indicator (ARSSI) signal indicative of signal strength of the analog signal after its amplification;

a processing part operable to assess on an ongoing basis how a measured performance attribute at the demodulator compares with a minimum value of that performance attribute required to satisfy the standard, thereby to determine an operating margin; and

a control output connected to a control input of at least one component in the analog front end and operable to output a front-end control signal based on the operating margin and the ARSSI signal.


  5. The receiver of claim 4, wherein the performance attribute is, or is derived from, one or more of baseband signal-to-noise ratio, and noise factor.
  6. The receiver of claim 4 or 5, wherein the at least one amplifier has a gain which is controlled in use according to the front-end control signal.
  7. The receiver of claim 4, 5, or 6, wherein the ADC has a bit resolution which is variable and controlled in use according to the front-end control signal.
  8. The receiver of claim 4, 5, 6 or 7, wherein the ADC is operated with an ADC sampling frequency which is controlled in use according to the front-end control signal.
  9. The receiver of any one of the preceding claims, further comprising an antenna connected to the analog signal input for receiving the analog signal wirelessly.
  10. A transceiver comprising a receiver according to any one of the preceding claims and a transmitter having a digital part, including a modulator, integrated with the receiver's digital decoder, and an analog part integrated with the receiver's analog front end.
  11. A wireless personal area network comprising a plurality of transceivers according to claim 10 each arranged in operative wireless communication with at least one other of the transceivers.
  12. A method of decoding digital data from an analog signal known to conform to a particular standard, the method comprising:

(i) receiving (S160) the analog signal;

(ii) amplifying (S162) the analog signal;

(iii) converting (S164) the analog signal into a digital signal; and

(iv) demodulating the digital signal at a chip frequency set by a clock signal, wherein the chip frequency corresponds to the frequency of the bits in the received signal

wherein the demodulating is carried out by:

(a) sampling (S166) the digital signal at a sampling frequency which is a multiple of the chip frequency;

(b) applying (S168) a double correlation function to process a set of bits, referred to as a symbol, in the sampled digitised signal to compute a set of correlation values, wherein the set of correlation values is an indicator of likely mapping between the symbol that has been processed and a set of possible symbols defined according to the standard, wherein the double correlation function is performed over two dimensions comprising a number of bits per chip-code and a lag delay of the set of bits; and

(c) deciding (S 170) which chip-code, referred to as a symbol, has been received based on an analysis of each set of correlation values,

wherein the chip frequency is adjusted momentarily (S172) dependent upon the correlation values by increasing or decreasing the chip frequency for an amount of time based on a measurement of whether the maximum correlation value among each set of correlation values occurs earlier or later than predicted according to the chip frequency currently in use.