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1. EP3965143 - PREPARATION METHOD FOR SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE

Office
European Patent Office
Application Number 21802178
Application Date 24.05.2021
Publication Number 3965143
Publication Date 09.03.2022
Publication Kind A1
IPC
H01L 21/28
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
CPC
H01L 21/28247
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
28008Making conductor-insulator-semiconductor electrodes
28017the insulator being formed after the semiconductor body, the semiconductor being silicon
28247passivation or protection of the electrode, e.g. using re-oxidation
H01L 21/28061
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
28008Making conductor-insulator-semiconductor electrodes
28017the insulator being formed after the semiconductor body, the semiconductor being silicon
28026characterised by the conductor
28035the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
28044the conductor comprising at least another non-silicon conductive layer
28061the conductor comprising a metal or metallic silicode formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
H01L 29/401
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
401Multistep manufacturing processes
H01L 29/4983
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
43characterised by the materials of which they are formed
49Metal-insulator-semiconductor electrodes, ; e.g. gates of MOSFET
4983with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
H01L 29/4941
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
43characterised by the materials of which they are formed
49Metal-insulator-semiconductor electrodes, ; e.g. gates of MOSFET
4916the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
4925with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
4941with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
H01L 29/49
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
43characterised by the materials of which they are formed
49Metal-insulator-semiconductor electrodes, ; e.g. gates of MOSFET
Applicants CHANGXIN MEMORY TECH INC
Inventors WU GONGYI
YU YOUQUAN
LU YONG
Designated States
Title
(DE) HERSTELLUNGSVERFAHREN FÜR HALBLEITERSTRUKTUR UND HALBLEITERSTRUKTUR
(EN) PREPARATION METHOD FOR SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE
(FR) PROCÉDÉ DE PRÉPARATION POUR UNE STRUCTURE SEMI-CONDUCTRICE ET STRUCTURE SEMI-CONDUCTRICE
Abstract
(EN) The application provides a method for manufacturing a semiconductor structure and a semiconductor structure. The method for manufacturing the semiconductor structure includes the following operations. A first conductive layer, a second conductive layer and a passivation layer are successively formed on a semiconductor substrate. The passivation layer and the second conductive layer are patterned to form a primary gate pattern, A portion of the first conductive layer that is not covered by the primary gate pattern, is exposed. The primary gate pattern is subjected with plasma treatment to form a first protective layer on a side wall of the second conductive layer. A dielectric layer is formed on a side wall of the primary gate pattern and a side surface of the first protective layer. The exposed portion of the first conductive layer is removed to retain a portion of the first conductive layer covered by the primary gate pattern. A second protective layer is formed on a side wall of the exposed portion of the first conductive layer. The second protective layer and the dielectric layer serve as an isolation layer of the gate structure.
(FR) La présente invention concerne un procédé de préparation pour une structure semi-conductrice et la structure semi-conductrice. Le procédé de préparation pour la structure semi-conductrice comprend les étapes suivantes consistant à : former séquentiellement une première couche conductrice, une seconde couche conductrice et une couche de passivation sur un substrat semi-conducteur ; former des motifs sur la couche de passivation et la seconde couche conductrice pour former un motif de porte primaire, laissant une zone de la première couche conductrice non recouverte par le motif de porte primaire exposé ; exécuter un traitement par plasma sur le motif de porte primaire pour former une première couche de protection sur la paroi latérale de la seconde couche conductrice ; former une couche diélectrique sur la paroi latérale du motif de porte primaire et la surface latérale de la première couche de protection ; éliminer la zone exposée de la première couche conductrice, et réserver la zone de la première couche conductrice recouverte par le motif de porte primaire ; et former une seconde couche de protection sur la paroi latérale exposée de la première couche conductrice, la seconde couche de protection et la couche diélectrique étant utilisées en tant que couche d'isolation d'une structure de porte.
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