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1. EP3776870 - SCHEDULING FOR LAYERED DECODING OF LOW-DENSITY PARITY-CHECK (LDPC) CODES

Office European Patent Office
Application Number 19717078
Application Date 28.03.2019
Publication Number 3776870
Publication Date 17.02.2021
Publication Kind A1
IPC
H03M 13/11
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING, DECODING OR CODE CONVERSION, IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11using multiple parity bits
CPC
H03M 13/114
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11using multiple parity bits
1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
1105Decoding
1131Scheduling of bit node or check node processing
114Shuffled, staggered, layered or turbo decoding schedules
H03M 13/116
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11using multiple parity bits
1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
1148Structural properties of the code parity-check or generator matrix
116Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
H03M 13/6306
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
63Joint error correction and other techniques
6306Error control coding in combination with Automatic Repeat reQuest [ARQ] and diversity transmission, e.g. coding schemes for the multiple transmission of the same information or the transmission of incremental redundancy
H03M 13/6362
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
63Joint error correction and other techniques
635Error control coding in combination with rate matching
6362by puncturing
H03M 13/6393
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
63Joint error correction and other techniques
635Error control coding in combination with rate matching
6362by puncturing
6368using rate compatible puncturing or complementary puncturing
6393Rate compatible low-density parity check [LDPC] codes
H03M 13/1128
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11using multiple parity bits
1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
1105Decoding
1128Judging correct decoding and iterative stopping criteria other than syndrome check and upper limit for decoding iterations
Applicants QUALCOMM INC
Inventors WANG YING
JIANG JING
BLACK PETER JOHN
SORIAGA JOSEPH BINAMIRA
SARKIS GABI
Designated States
Priority Data 201862650705 30.03.2018 US
16366997 27.03.2019 US
Title
(DE) ABLAUFSTEUERUNG ZUR SCHICHTDECODIERUNG VON LOW DENSITY PARITY CHECK (LDPC)-CODES
(EN) SCHEDULING FOR LAYERED DECODING OF LOW-DENSITY PARITY-CHECK (LDPC) CODES
(FR) PLANIFICATION POUR DÉCODAGE EN COUCHES DE CODES DE CONTRÔLE DE PARITÉ À FAIBLE DENSITÉ (LDPC)
Abstract
(EN)
Methods, systems, and devices for wireless communications are described. Efficient low-density parity-check (LDPC) scheduling of layered decoding may include receiving a message encoded as an LDPC code that includes a number of check nodes and a number of bit nodes, applying a first number of decoding iterations to decoding the message, applying a second number of decoding iterations to decoding the message after the first number of decoding iterations are applied, and decoding the message through completion of both the first number of decoding iterations and the second number of decoding iterations. In some cases, only a portion of the number of check nodes is decoded during each of the first number of decoding iterations (partial decoding) and all of the number of check nodes are decoded during each of the second number of decoding iterations. The scheduling order may be based on the check node degree (starting with the lowest degree) or on a number of punctured bit nodes connected to the check nodes.

(FR)
L’invention concerne des procédés, des systèmes et des dispositifs destinés à des communications sans fil. Une planification efficace de contrôle de parité à faible densité (LDPC) de décodage en couches peut comprendre la réception d'un message codé sous la forme d'un code LDPC qui comprend un certain nombre de nœuds de contrôle et un certain nombre de nœuds de bits, l'application d'un premier nombre d'itérations de décodage pour décoder le message, l'application d'un second nombre d'itérations de décodage pour décoder le message après l'application du premier nombre d'itérations de décodage, et le décodage du message par l'exécution à la fois du premier nombre d'itérations de décodage et du second nombre d'itérations de décodage. Dans certains cas, seule une partie du nombre de nœuds de contrôle est décodée pendant chaque itération du premier nombre d'itérations de décodage (décodage partiel) et la totalité du nombre de nœuds de contrôle est décodée pendant chaque itération du second nombre d'itérations de décodage. L'ordre de planification peut être basé sur le degré de nœud de contrôle (en commençant par le degré le plus bas) ou sur un nombre de nœuds de bits poinçonnés connectés aux nœuds de contrôle.