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1. (EP2377155) SYSTEM AND METHOD FOR ISOLATED NMOS-BASED ESD CLAMP CELL

Office : European Patent Office
Application Number: 09835498 Application Date: 07.12.2009
Publication Number: 2377155 Publication Date: 19.10.2011
Publication Kind : A4
Designated States: AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR
Prior PCT appl.: Application Number:US2009066984 ; Publication Number: Click to see the data
IPC:
H01L 23/62
H01L 27/02
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
58
Structural electrical arrangements for semiconductor devices not otherwise provided for
62
Protection against overcurrent or overload, e.g. fuses, shunts
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
CPC:
H01L 27/0266
H01L 2224/48091
H01L 2224/48464
H01L 2924/1305
H01L 2924/13091
Applicants: ANALOG DEVICES INC
Inventors: FOLEY DAVID
ZHU HAIYANG
Priority Data: 12285508 16.12.2008 US
2009066984 07.12.2009 US
53498809 04.08.2009 US
Title: (DE) SYSTEM UND VERFAHREN FÜR ISOLIERTE ESD-KLEMMZELLE AUF NMOS-BASIS
(EN) SYSTEM AND METHOD FOR ISOLATED NMOS-BASED ESD CLAMP CELL
(FR) SYSTÈME ET PROCÉDÉ POUR UNE PINCE DE PROTECTION CONTRE LES DÉCHARGES ÉLECTROSTATIQUES À PARTIR D'UN SEMI-CONDUCTEUR NMOS ISOLÉ
Abstract:
(EN) The invention is directed to a protection circuit for protecting IC chips against ESD. An ESD protection circuit for an integrated circuit chip may comprise an isolated NMOS transistor, which may comprise an isolation region isolating a backgate from a substrate, and a first and second doped regions and a gate formed on the backgate. The ESD protection circuit may further comprise a first terminal to connect the isolation region to a first electrical node, and a second terminal to connect the second doped region to a second electrical node. The first electrical node may have a higher voltage level than the second electrical node, and the gate and backgate may be coupled to the second terminal.
(FR) Cette invention concerne un circuit de protection pour protéger les puces de circuit intégré (CI) contre les décharges électrostatiques (ESD). Un circuit de protection ESD pour une puce CI peut comprendre un transistor NMOS isolé, qui peut comprendre une zone d'isolation isolant un matériau de base d'un substrat, ainsi qu'une première et une seconde région dopée, et une porte formée sur le matériau de base. Le circuit de protection ESD peut en outre comprendre un premier terminal pour relier la zone d'isolation à un premier nœud électrique, et un second terminal pour relier la seconde région dopée à un second nœud électrique. Le premier nœud électrique peut avoir un niveau de tension supérieur à celui du second nœud électrique, et la porte et le matériau de base peuvent être couplés au second terminal.
Also published as:
JP2012512544CN102292813WO/2010/074939