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1. EP3577847 - CLOCK DATA RECOVERY WITH NON-UNIFORM CLOCK TRACKING

Office
European Patent Office
Application Number 18703401
Application Date 12.01.2018
Publication Number 3577847
Publication Date 11.12.2019
Publication Kind B1
IPC
H04L 7/00
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7Arrangements for synchronising receiver with transmitter
H03L 7/081
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7Automatic control of frequency or phase; Synchronisation
06using a reference signal applied to a frequency- or phase-locked loop
08Details of the phase-locked loop
081provided with an additional controlled phase shifter
H04L 7/033
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7Arrangements for synchronising receiver with transmitter
02Speed or phase control by the received code signals, the signals containing no special synchronisation information
033using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
CPC
H04L 7/0025
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7Arrangements for synchronising receiver with transmitter
0016correction of synchronization errors
002correction by interpolation
0025interpolation of clock signal
H04L 7/0337
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7Arrangements for synchronising receiver with transmitter
02Speed or phase control by the received code signals, the signals containing no special synchronisation information
033using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
0337Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
H03L 2207/50
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
2207Indexing scheme relating to automatic control of frequency or phase and to synchronisation
50All digital phase-locked loop
H04L 25/03273
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
25Baseband systems
02Details
03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
03006Arrangements for removing intersymbol interference
03178Arrangements involving sequence estimation techniques
03248Arrangements for operating in conjunction with other apparatus
03273with carrier recovery circuitry
H04L 43/16
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
43Arrangements for monitoring or testing packet switching networks
16using threshold monitoring
H04L 2027/0069
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
27Modulated-carrier systems
0014Carrier regulation
0044Control loops for carrier regulation
0063Elements of loops
0069Loop filters
Applicants QUALCOMM INC
Inventors SONG YU
ZHU ZHI
LI MIAO
SUN LI
SONG DEQIANG
CHANG CHIA HENG
Designated States
Priority Data 15422050 01.02.2017 US
Title
(DE) TAKTDATENWIEDERHERSTELLUNG MIT UNGLEICHMÄSSIGER TAKTVERFOLGUNG
(EN) CLOCK DATA RECOVERY WITH NON-UNIFORM CLOCK TRACKING
(FR) RÉCUPÉRATION DE DONNÉES D'HORLOGE AVEC SUIVI D'HORLOGE NON UNIFORME
Abstract
(EN) Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).
(FR) Selon certains aspects, la présente invention concerne des systèmes et des procédés permettant de régler une longueur de créneau de phase d'un circuit de récupération de données d'horloge (CDR). Selon certains aspects, un procédé de réglage d'une longueur de créneau de phase d'un circuit CDR comprend la détection d'un décalage de fréquence du circuit CDR, et le réglage de la longueur de créneau du circuit CDR sur la base du décalage de fréquence détecté. Le décalage de fréquence peut être détecté par détection d'un niveau de signal sur un trajet d'intégration d'un filtre à boucle du circuit CDR. La longueur de créneau de phase du circuit CDR peut être réglée par commutation du circuit CDR entre une première longueur de créneau de phase et une seconde longueur de créneau de phase à l'aide d'un modulateur (par exemple, un modulateur sigma-delta).