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1. (EP3036835) ENHANCED AUTOMATIC IDENTIFICATION SYSTEM

Office : European Patent Office
Application Number: 14838624 Application Date: 22.08.2014
Publication Number: 3036835 Publication Date: 29.06.2016
Publication Kind : A4
Designated States: AL, AT, BA, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, ME, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR
Prior PCT appl.: Application Number:AU2014000832 ; Publication Number: Click to see the data
IPC:
G06F 11/10
H03M 5/14
H03M 13/09
H03M 13/11
H03M 13/23
H03M 13/29
H03M 13/31
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
11
Error detection; Error correction; Monitoring
07
Responding to the occurrence of a fault, e.g. fault tolerance
08
Error detection or correction by redundancy in data representation, e.g. by using checking codes
10
Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
M
CODING, DECODING OR CODE CONVERSION, IN GENERAL
5
Conversion of the form of the representation of individual digits
02
Conversion to or from representation by pulses
04
the pulses having two levels
14
Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
M
CODING, DECODING OR CODE CONVERSION, IN GENERAL
13
Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03
Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05
using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
09
Error detection only, e.g. using cyclic redundancy check (CRC) codes or single parity bit
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
M
CODING, DECODING OR CODE CONVERSION, IN GENERAL
13
Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03
Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05
using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11
using multiple parity bits
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
M
CODING, DECODING OR CODE CONVERSION, IN GENERAL
13
Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03
Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
23
using convolutional codes, e.g. unit memory codes
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
M
CODING, DECODING OR CODE CONVERSION, IN GENERAL
13
Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
29
combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
M
CODING, DECODING OR CODE CONVERSION, IN GENERAL
13
Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
31
combining coding for error detection or correction and efficient use of the spectrum
CPC:
H03M 5/145
H03M 13/09
H03M 13/1102
H03M 13/23
H03M 13/2957
H03M 13/31
H03M 13/6325
H03M 13/6356
H04L 1/00
H04L 1/0041
H04L 1/0045
H04L 1/0061
H04L 1/0071
Applicants: UNIV SOUTH AUSTRALIA
Inventors: GRANT ALEXANDER JAMES
LECHNER GOTTFRIED
POLLOK ANDRE
MCKILLIAM ROBERT GEORGE
LAND INGMAR RUDIGER
HALEY DAVID VICTOR LAWRIE
LAVENANT MARC PIERRE DENIS
Priority Data: 2013903219 23.08.2013 AU
2014000832 22.08.2014 AU
Title: (DE) VERBESSERTES AUTOMATISCHES IDENTIFIZIERUNGSSYSTEM
(EN) ENHANCED AUTOMATIC IDENTIFICATION SYSTEM
(FR) SYSTÈME D'AUTHENTIFICATION AUTOMATIQUE AMÉLIORÉ
Abstract:
(EN) The invention relates to method and apparatus for improving the performance of communication systems using Run Length Limited (RLL) messages such as the existing Automatic Identification System (AlS). A binary data sequence is Forward Error Correction (FEC) coded and then the sequence is compensated, for example by bit-erasure, so that either bit-stuffing is not required, or a bit stuffer will not be activated to ensure that the coded sequence meets the RLL requirement. Various embodiments are described to handle different architectures or input points for the FEC encoder and bit erasure module. The bit erasure module may also add dummy bits to ensure a RLL compliant CRC or to selectively add bits to a reserve buffer to compensate for later bit stuffing in a header. Additional RLL training sequences may also be added to assist in, receiver acquisition.
(FR) L'invention concerne un procédé et un appareil pour améliorer les performances de systèmes de communication employant des messages à longueur de course limitée (RLL) tels que les systèmes d'identification automatique (AlS) existants. Une séquence de données binaires est codée avec correction d'erreur directe (FEC) et la séquence est ensuite compensée, par exemple par effacement de bit, de sorte que soit le bourrage de bits n'est pas nécessaire, soit un dispositif de bourrage de bits ne sera pas activé afin de garantir que la séquence codée satisfait aux exigences de RLL. Différents modes de réalisation sont décrits pour traiter différentes architectures ou points d'entrée pour le codeur FEC et le module d'effacement des bits. Le module d'effacement des bits peut également ajouter des bits factices pour garantir un CRC conforme RLL ou ajouter de manière sélective des bits à un tampon de réserve afin de compenser le futur bourrage de bits dans un en-tête. Des séquences d'apprentissage RLL supplémentaires peuvent également être ajoutées pour assister dans l'acquisition du récepteur.
Also published as:
CA2920298US20160277145JP2016533682AU2014308554AU2018226442WO/2015/024062