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1. (EP3036768) LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION

Office : European Patent Office
Application Number: 14758472 Application Date: 21.08.2014
Publication Number: 3036768 Publication Date: 29.06.2016
Publication Kind : B1
Designated States: AL, AT, BA, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, ME, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR
Prior PCT appl.: Application Number:US2014052020 ; Publication Number: Click to see the data
IPC:
H01L 27/02
H01L 21/8238
H01L 23/482
H01L 23/522
H01L 23/528
H01L 27/092
H03K 17/16
H03K 17/687
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8238
Complementary field-effect transistors, e.g. CMOS
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
482
consisting of lead-in layers inseparably applied to the semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
528
Layout of the interconnection structure
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
08
including only semiconductor components of a single kind
085
including field-effect components only
088
the components being field-effect transistors with insulated gate
092
complementary MIS field-effect transistors
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
17
Electronic switching or gating, i.e. not by contact-making and -breaking
16
Modifications for eliminating interference voltages or currents
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
17
Electronic switching or gating, i.e. not by contact-making and -breaking
51
characterised by the use of specified components
56
by the use, as active elements, of semiconductor devices
687
the devices being field-effect transistors
CPC:
H01L 27/0921
H01L 21/823871
H01L 23/4824
H01L 23/522
H01L 23/535
H01L 27/0207
H01L 27/092
H01L 2924/0002
H03K 17/168
H03K 17/6872
H05K 999/99
Applicants: QUALCOMM INC
Inventors: RASOULI SEID HADI
DATTA ANIMESH
KWON OHSANG
Priority Data: 201313975074 23.08.2013 US
2014052020 21.08.2014 US
Title: (DE) LAYOUT-KONSTRUKTION ZUR ADRESSIERUNG VON ELEKTROMIGRATION
(EN) LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION
(FR) CONSTRUCTION TOPOLOGIQUE POUR ABORDER LE PROBLÈME D'ÉLECTROMIGRATION
Abstract: front page image
(EN) A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together though at least one other interconnect level.
(FR) Selon l'invention, une première interconnexion sur un niveau d'interconnexion connecte ensemble un premier sous-ensemble de drains PMOS d'un dispositif CMOS. Une deuxième interconnexion sur le niveau d'interconnexion connecte ensemble un deuxième sous-ensemble des drains PMOS. Le deuxième sous-ensemble des drains PMOS est différent du premier sous-ensemble des drains PMOS. La première interconnexion et la deuxième interconnexion sont déconnectées sur le niveau d'interconnexion. Une troisième interconnexion sur le niveau d'interconnexion connecte ensemble un premier sous-ensemble de drains NMOS du dispositif CMOS. Une quatrième interconnexion sur le niveau d'interconnexion connecte ensemble un deuxième sous-ensemble des drains NMOS. Le deuxième sous-ensemble des drains NMOS est différent du premier sous-ensemble des drains NMOS. La troisième interconnexion et la quatrième interconnexion sont déconnectées sur le niveau d'interconnexion. Les première, deuxième, troisième et quatrième interconnexions sont couplées l'une à l'autre par l'intermédiaire d'au moins un autre niveau d'interconnexion.
Also published as:
CN105474393JP2016535454IN201647001908JP2018014507WO/2015/027025