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1. (EP1920466) SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR-ON-INSULATOR (SOI) CONFIGURATION AND INCLUDING A SUPERLATTICE ON A THIN SEMICONDUCTOR LAYER AND ASSOCIATED METHODS

Office : European Patent Office
Application Number: 06786244 Application Date: 30.06.2006
Publication Number: 1920466 Publication Date: 14.05.2008
Publication Kind : A1
Designated States: DE, FR, GB, IT
Prior PCT appl.: Application Number:US2006026029 ; Publication Number: Click to see the data
IPC:
H01L 29/15
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
15
Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
CPC:
H01L 29/78696
B82Y 10/00
H01L 29/04
H01L 29/1054
H01L 29/151
H01L 29/78681
Applicants: MEARS TECHNOLOGIES INC
Inventors: RAO KALIPATNAM VIVEK
Priority Data: 2006026029 30.06.2006 US
69558805 30.06.2005 US
Title: (DE) HALBLEITERANORDNUNG MIT EINER KONFIGURATION AUS HALBLEITER-AUF-ISOLATOR (SOI) UND MIT EINEM SUPERGITTER AUF EINER DÜNNEN HALBLEITERSCHICHT UND ASSOZIIERTE VERFAHREN
(EN) SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR-ON-INSULATOR (SOI) CONFIGURATION AND INCLUDING A SUPERLATTICE ON A THIN SEMICONDUCTOR LAYER AND ASSOCIATED METHODS
(FR) DISPOSITIF SEMI-CONDUCTEUR AYANT UNE CONFIGURATION SEMI-CONDUCTEUR SUR ISOLANT (SOI), COMPRENANT UN SUPER-RÉSEAU SUR UNE COUCHE SEMI-CONDUCTRICE ET PROCÉDÉS ASSOCIÉS
Abstract:
(EN) A semiconductor device may include a substrate, an insulating layer on the substrate, and a semiconductor layer on the insulating layer on a side thereof opposite the substrate. The semiconductor device may further include a superlattice on the semiconductor layer on a side thereof opposite the insulating layer. The superlattice may include a plurality of stacked groups of layers, with each group comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions.
(FR) La présente invention concerne un dispositif semi-conducteur pouvant comprendre un substrat, une couche isolante sur le substrat et une couche semi-conductrice sur la couche isolante sur un côté de celle-ci opposé au substrat. Le dispositif semi-conducteur peut comprendre en outre un super-réseau sur la couche semi-conductrice sur un côté de celle-ci opposé à la couche isolante. Le super-réseau peut comprendre une pluralité de groupes empilés de couches, chaque groupe comprenant une pluralité de monocouches semi-conductrices de base empilées définissant une partie semi-conductrice de base et au moins une monocouche non semi-conductrice sur celle-ci. La monocouche non semi-conductrice peut être contrainte dans un réseau cristallin de parties semi-conductrices de base adjacentes.
Also published as:
JP2008544581CN101278400CA2612243AU2006265096WO/2007/005862