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1. (EP1410399) METHOD AND APPARATUS FOR DECREASING BLOCK WRITE OPERATION TIMES PERFORMED ON NONVOLATILE MEMORY

Office : European Patent Office
Application Number: 00939691 Application Date: 09.06.2000
Publication Number: 1410399 Publication Date: 21.04.2004
Publication Kind : B1
Designated States: DE, FR, GB
Prior PCT appl.: Application Number:US2000015777 ; Publication Number: Click to see the data
IPC:
G06F 12/02
G11C 16/02
G06F 3/06
G06F 11/10
G06F 12/00
G11C 8/12
G11C 16/08
G11C 16/10
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
02
Addressing or allocation; Relocation
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
3
Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06
Digital input from, or digital output to, record carriers
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
11
Error detection; Error correction; Monitoring
07
Responding to the occurrence of a fault, e.g. fault tolerance
08
Error detection or correction by redundancy in data representation, e.g. by using checking codes
10
Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
8
Arrangements for selecting an address in a digital store
12
Group selection circuits, e.g. for memory block selection, chip selection, array selection
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
06
Auxiliary circuits, e.g. for writing into memory
08
Address circuits; Decoders; Word-line control circuits
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
06
Auxiliary circuits, e.g. for writing into memory
10
Programming or data input circuits
CPC:
G11C 16/102
G06F 3/0616
G06F 3/064
G06F 3/0679
G06F 11/1068
G06F 12/0246
G11C 8/12
G11C 16/08
Applicants: LEXAR MEDIA INC
Inventors: ESTAKHRI PETRO
IMAN BEHANU
Priority Data: 0015777 09.06.2000 US
33027899 11.06.1999 US
Title: (DE) VERFAHREN UND SCHALTUNG ZUR VERKÜRZUNG DER BLOCKSCHREIBZEIT BEI EINEM NICHT-FLÜCHTIGEN SPEICHER
(EN) METHOD AND APPARATUS FOR DECREASING BLOCK WRITE OPERATION TIMES PERFORMED ON NONVOLATILE MEMORY
(FR) PROCEDE ET DISPOSITIF PERMETTANT DE REDUIRE LA DUREE DE L'OPERATION D'ECRITURE BLOC DANS LE CAS D'UNE MEMOIRE NON VOLATILE
Abstract: front page image
(EN) A memory device comprises a controller (14) coupled to a host (12) and a nonvolatile memory unit (16) for controlling reading and writing information organized in sectors (34, 36) from and to the nonvolatile memory unit (16), as commanded by the host (12). The controller (14) maintains mapping of the sector information in an LUT stored in volatile memory the contents of which are lost if power is lost. Through the use of an address value and flag information maintained within each of the blocks of the nonvolatile memory unit (16), a block is re-written using a different number of write operation in various alternative embodiments of the present invention. The flag information is indicative of the status of the block such that during power-up, the controller (14) reads the address value and the flag information of a block and determines the status of the block and in accordance therewith finishes re-writing of the block, if necessary and updates the LUT accordingly.
(FR) La présente invention concerne un dispositif de mémoire comprenant un contrôleur (14) couplé à un hôte (12) et à une mémoire non volatile (16) de façon à commander la lecture et l'écriture des informations organisées en secteurs en provenance et à destination de cette mémoire non volatile (16), suivant ce qui est demandé par l'hôte (12). Le contrôleur (14) tient à jour les informations de secteurs dans une table de consultation conservée dans la mémoire volatile d'où l'information peut disparaître en cas de perte d'alimentation électrique. Grâce à l'utilisation d'une valeur d'adresse et d'une information sémaphore tenue à jour à l'intérieur de chacun des blocs de la mémoire non volatile (16), pour réécrire un bloc, le nombre d'opérations d'écriture est variable suivant les différentes réalisations de l'invention. L'information sémaphore permet de connaître l'état du bloc de façon qu'à la mise sous tension, une fois que le contrôleur (14) a lu la valeur d'adresse et l'information sémaphore d'un bloc, il peut déterminer l'état du bloc, et en fonction de ce qu'il connaît, il peut, le cas échéant achever la réécriture du bloc, et mettre à jour la table de consultation en conséquence.
Also published as:
JP2005516264AU2000054741WO/2000/077791