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1. EP1374248 - VERY SMALL SWING AND LOW VOLTAGE CMOS STATIC MEMORY

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Office European Patent Office
Application Number 01989977
Application Date 05.11.2001
Publication Number 1374248
Publication Date 02.01.2004
Publication Kind B1
IPC
G11C 11/419
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
417for memory cells of the field-effect type
419Read-write circuits
G11C 8/16
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
8Arrangements for selecting an address in a digital store
16Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
G11C 11/412
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
412using field-effect transistors only
CPC
G11C 7/02
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
02with means for avoiding parasitic signals
G11C 7/062
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
06Sense amplifiers; Associated circuits, ; e.g. timing or triggering circuits
062Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
G11C 7/067
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
06Sense amplifiers; Associated circuits, ; e.g. timing or triggering circuits
067Single-ended amplifiers
G11C 8/16
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
8Arrangements for selecting an address in a digital store
16Multiple access memory array, e.g. addressing one storage element via at least independent addressing line groups
G11C 11/412
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming ; static; cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
412using field-effect transistors only
G11C 11/413
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming ; static; cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction
Applicants BROADCOM CORP
Inventors SLAMOWITZ MARK
SMITH DOUGLAS D
BUER MYRON
Priority Data 0146942 05.11.2001 US
10012858 03.11.2001 US
24591300 03.11.2000 US
Title
(DE) CMOS SPEICHER MIT KLEINE SCHWANKENDE SPANNUNGEN UND MIT GERINGER BETRIEBSPANNUNG
(EN) VERY SMALL SWING AND LOW VOLTAGE CMOS STATIC MEMORY
(FR) MEMOIRE STATIQUE CMOS ASYNCHRONE PRESENTANT DES OSCILLATIONS TRES FAIBLES
front page image
Abstract
(EN)
The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously. The storage elements are arranged in rows and columns and store data. Two read port pairs are coupled to each of the storage elements and a differential sensing device or circuit. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A column mux circuit is coupled to each column and the sensing device. Performance is not degraded unusually as the power supply voltage is reduced due to bus drop or inductive effects.

(FR)
L'invention concerne une mémoire de pile à accès multiples ou SRAM comprenant une pluralité d'éléments de mémoire et d'autres circuits fonctionnant en mode synchrone ou asynchrone. Ces éléments de mémoire sont disposés en rangées et en colonnes et servent à mémoriser des données. Deux paires de points d'accès de lecture sont couplées à chacun des éléments de mémoire et à un circuit ou dispositif de détection différentielle. Ce point d'accès de lecture est couplé aux éléments de mémoire de façon isolée, ce qui permet de placer une pluralité de cellules dans ces rangées et ces colonnes. Le dispositif de détection est conçu pour détecter une faible oscillation de tension. Un circuit de multiplexage de colonnes est couplé à chaque colonne et au dispositif de détection. La baisse de tension d'alimentation provoquée par une chute du bus ou des effets inductifs ne dégrade pas anormalement les capacités de la mémoire.
Also published as
DE000060119583
US20020125585
US20040066687
US20050091477
US20080089144
US20100177581
WO/2002/043072
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