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1. EP1323301 - SYSTEM AND METHOD FOR SINGLE PIN RESET IN A MIXED SIGNAL INTEGRATED CIRCUIT

Office
European Patent Office
Application Number 01983083
Application Date 13.09.2001
Publication Number 1323301
Publication Date 02.07.2003
Publication Kind A2
IPC
H04N 5/14
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
NPICTORIAL COMMUNICATION, e.g. TELEVISION
5Details of television systems
14Picture signal circuitry for video frequency region
H04N 5/04
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
NPICTORIAL COMMUNICATION, e.g. TELEVISION
5Details of television systems
04Synchronising
H04N 5/12
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
NPICTORIAL COMMUNICATION, e.g. TELEVISION
5Details of television systems
04Synchronising
12Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising
H04N 5/44
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
NPICTORIAL COMMUNICATION, e.g. TELEVISION
5Details of television systems
44Receiver circuitry
H04N 5/46
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
NPICTORIAL COMMUNICATION, e.g. TELEVISION
5Details of television systems
44Receiver circuitry
46for receiving on more than one standard at will
CPC
H04N 5/04
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
NPICTORIAL COMMUNICATION, e.g. TELEVISION
5Details of television systems
04Synchronising
H04N 5/126
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
NPICTORIAL COMMUNICATION, e.g. TELEVISION
5Details of television systems
04Synchronising
12Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising
126whereby the synchronisation signal indirectly commands a frequency generator
H04N 5/46
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
NPICTORIAL COMMUNICATION, e.g. TELEVISION
5Details of television systems
44Receiver circuitry ; for the reception of television signals according to analogue transmission standards;
46for receiving on more than one standard at will
H04N 21/426
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
NPICTORIAL COMMUNICATION, e.g. TELEVISION
21Selective content distribution, e.g. interactive television or video on demand [VOD]
40Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
41Structure of client; Structure of client peripherals
426Internal components of the client ; ; Characteristics thereof;
Applicants THOMSON LICENSING SA
Inventors ALBEAN DAVID LAWRENCE
Designated States
Priority Data 0128441 13.09.2001 US
09666021 19.09.2000 US
Title
(DE) SYTEM UND VERFAHREN ZUM EINZELKONTAKTRÜCKSETZEN FÜR EINEN INTERGRIERTEN GEMICHTSIGNALSCHALTKREIS
(EN) SYSTEM AND METHOD FOR SINGLE PIN RESET IN A MIXED SIGNAL INTEGRATED CIRCUIT
(FR) SYSTEME ET PROCEDE DE REMISE A ZERO D'UNE BROCHE UNIQUE DANS UN CIRCUIT INTEGRE A SIGNAUX MIXTES
Abstract
(EN)
A system and method is described for providing a single pin reset for a mixed signal integrated circuit. The system and method provides for a single reset signal/pin of the integrated circuit to be utilized to generate all internal resets for the analog and digital circuitry/sections of the mixed signal integrated circuit. In one form, a state machine generates a reset signal for a phase locked loop synthesizer that is utilized to generate internal system clocks for the analog and digital circuitry, as well as a digital reset signal that provides reset signals to the various digital sections circuitry of the integrated circuit. Preferably, the chip reset signal is provided for a longer period of time than the PLL reset signal in order to assure that the PLL is running and generating clocking signals before the digital logic is clocked.

(FR)
L'invention concerne un système et un procédé permettant la remise à zéro d'une broche unique pour un circuit intégré à signaux mixtes. Le système et le procédé décrits dans cette invention consistent en une broche/signal de remise à zéro unique du circuit intégré pouvant être utilisé pour exécuter toutes les remises à zéro internes de l'ensemble des circuits / des sections analogiques et numériques du circuit intégré à signaux mixtes. Dans un mode de réalisation, un automate produit un signal de remise à zéro pour un synthétiseur à boucle à asservissement de phase (PLL) utilisé pour produire des horloges système internes pour l'ensemble de circuits analogiques et numériques, ainsi qu'un signal de remise à zéro numérique fournissant des signaux de remise à zéro aux différentes sections numériques de l'ensemble des circuits du circuit intégré. De préférence, le signal de remise à zéro de la puce est fourni plus longtemps que le signal de remise à zéro PLL, de manière à garantir que la boucle à asservissement de phase fonctionne et qu'elle produise des signaux d'horloge avant que la logique numérique ne soit minutée.