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1. EP0860052 - AN INPUT/OUTPUT DRIVER CIRCUIT FOR ISOLATING WITH MINIMAL POWER CONSUMPTION A PERIPHERAL COMPONENT FROM A CORE SECTION

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Claims

1. An integrated circuit comprising:
   a single monolithic circuit (200) comprising a core section (203), an input/output driver circuit (404,406) and an input/output pad (502), said input/output driver circuit being interposed between said core section and said input/output pad, wherein said input/output driver circuit includes:

a pull-down transistor (510) connected between a ground (506) and said input/output pad, a gate of said pull-down transistor being connected to receive a signal during times in which a partial reset is detected,

a driving-high transistor (500) connected between a first power source (501) and said input/output pad, and

a driving-low transistor (505) connected between said ground and said input/output pad;

    characterised in that
   a pair of level translator/predriver circuits (503,507) is connected to respective gate terminals of said driving-high and driving-low transistors, wherein one of said level translator/predriver circuits is coupled to receive an output signal from said core section and to activate said driving-high transistor coupled thereto.
  2. The integrated circuit as claimed in claim 1, further comprising a pull-up transistor (508) connected between the first power source and said input/output pad, whereby the pull-up transistor is turned off during times in which said partial reset is detected.
  3. The integrated circuit as claimed in claim 2, wherein said pull-up transistor is turned on during times in which said partial reset is not detected.
  4. The integrated circuit as claimed in any of claims 1 to 3, wherein activating said driving-high transistor causes coupling of said first power source to said input/output pad.
  5. The integrated circuit as claimed in any of claims 1 to 4, wherein activating said driving-low transistor causes coupling of said ground to said input/output pad.
  6. The integrated circuit as claimed in any of claims 1 to 5, wherein said input/output pad is electrically coupled to a lead extending from a package surrounding said integrated circuit.
  7. The integrated circuit as claimed in any of claims 1 to 6, further comprising a plurality of input/output driver circuits within an input/output section, each input/output driver circuit being coupled between a portion of said core and a respective input/output pad.
  8. The integrated circuit as claimed in any of claims 1 to 7 in which a clamp circuit (514) is provided to limit the voltage on said input/output pad.
  9. The integrated circuit as claimed in claim 8, wherein said clamp circuit comprises:

a first diode arranged between a source terminal of said driving-high transistor and a second power source (504); and

a second diode arranged between a drain terminal of said driving-high transistor and said second power source.


  10. The integrated circuit as claimed in any of claims 1 to 9 including means for permitting deactivation of said first and second power sources and for activating said pull-down transistor at substantially the same time as said first and second power sources are deactivated.
  11. The integrated circuit as claimed in claims 9 and 10, wherein said deactivation permitting means comprises a switch within a power supply which provides said first and second power sources, said switch being adapted for disconnecting said first and second power sources from said driving-high transistor.
  12. The integrated circuit as claimed in claims 10 and 11, wherein said deactivation permitting means comprises a circuit within said core which produces a force term signal responsive to user input upon a pair of input pins configured upon said integrated circuit.