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1. (EP0527780) SCALER FOR SYNCHRONOUS DIGITAL CLOCK.

Office : European Patent Office
Application Number: 91907947 Application Date: 24.04.1991
Publication Number: 0527780 Publication Date: 24.02.1993
Publication Kind : B1
Prior PCT appl.: Application Number:CA1991000132 ; Publication Number: Click to see the data
IPC:
H 03K
H 03K
H03K 23/48
H03K 23/50
H03K 23/64
H03K 23/66
H03K 23/68
H03L 7/197
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
23
Pulse counters comprising counting chains; Frequency dividers comprising counting chains
64
with a base or radix other than a power of two
66
with a variable counting base, e.g. by presetting or by adding or suppressing pulses
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
23
Pulse counters comprising counting chains; Frequency dividers comprising counting chains
64
with a base or radix other than a power of two
68
with a base which is a non-integer
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
23
Pulse counters comprising counting chains; Frequency dividers comprising counting chains
40
Gating or clocking signals applied to all stages, i.e. synchronous counters
48
with a base or radix other than a power of two
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
23
Pulse counters comprising counting chains; Frequency dividers comprising counting chains
40
Gating or clocking signals applied to all stages, i.e. synchronous counters
50
using bi-stable regenerative trigger circuits
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
23
Pulse counters comprising counting chains; Frequency dividers comprising counting chains
64
with a base or radix other than a power of two
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
23
Pulse counters comprising counting chains; Frequency dividers comprising counting chains
64
with a base or radix other than a power of two
66
with a variable counting base, e.g. by presetting or by adding or suppressing pulses
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
23
Pulse counters comprising counting chains; Frequency dividers comprising counting chains
64
with a base or radix other than a power of two
68
with a base which is a non-integer
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
L
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7
Automatic control of frequency or phase; Synchronisation
06
using a reference signal applied to a frequency- or phase-locked loop
16
Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
18
using a frequency divider or counter in the loop
197
a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
CPC:
H03K 23/507
H03K 23/667
H03K 23/68
Applicants: NORTHERN TELECOM LTD
Inventors: SASAKI LAWRENCE HIROMI WEST RI
CHAN SUN-SHIU DAVID
Priority Data: 9100132 24.04.1991 CA
07524398 11.05.1990 US
Title: (DE) IMPULSFREQUENZTEILER FÜR EINEN SYNCHRONEN DIGITALEN TAKT.
(EN) SCALER FOR SYNCHRONOUS DIGITAL CLOCK.
(FR) DEMULTIPLICATEUR POUR HORLOGE NUMERIQUE SYNCHRONE.
Abstract: front page image
(EN) A scaler comprising a plurality of flip-flops (31-34), varies its frequency division to correct phase by 0.5 clock cycle. Each flip-flop (31-34) is continuously and synchronously responsive to either a rising (31, 33) or a falling (32, 34) edge of the clock pulses (CK). Normally, the scaler's state transits along one of two loops, which generate output pulses having identical repetition rates. When a control signal (X, Y) is applied, the scaler's state transits from one loop to the other, generating at least one output at an alternative repetition rate. The alternative repetition rate is either lower or higher than the identical repetition rate by an integral number of half cycles of the input clock pulses (CK). Where there are two control signals (X, Y) a lower or higher alternative repetition rate can be selected. Since the flip-flops (31-34) are responsive to either edge of the clock pulses (CK) without clock gating interruptions, there is no jitter and the scaler's robustness is improved. Also the clock frequency can be effectively halved.
(FR) Un démultiplicateur comprenant une multiplicité de bascules (31-34) varie sa division de fréquence pour corriger la phase à un rythme correspondant à 0,5 cycle d'horloge. Chaque bascule (31-34) répond en continu et de manière synchrone soit à un flanc ascendant (31, 33), soit à un flanc descendant (32, 34) des impulsions d'horloge (CK). En général, l'état du démultiplicateur voyage le long d'une des deux boucles, ce qui produit des impulsions de sortie possédant des fréquences de répétition identiques. Lorsqu'un signal de commande (X, Y) est appliqué, l'état du démultiplicateur voyage d'une boucle à l'autre, produisant au moins une sortie à une fréquence de répétition alternative. La fréquence de répétition alternative est soit inférieure, soit supérieure à la fréquence de répétition identique par un nombre entier de demi-cycles des impulsions d'horloge d'entrée (CK). Là où il y a deux signaux de commande (X, Y), une fréquence de répétition alternative supérieure ou inférieure peut être choisie. Puisque les bascules (31-34) répondent à n'importe lequel des flancs des impulsions d'horloge (CK) sans interruptions de déclenchement d'horloge, il n'y a pas d'instabilité et la robustesse du démultiplicateur est améliorée. La fréquence d'horloge peut aussi être efficacement diminuée de moitié.
Also published as:
JPH05506757CA2076960WO/1991/018449