(EN) The invention discloses a flip chip on-chip package and a manufacturing method thereof. The flip chip on-chip package comprises a lead frame, a first metal material layer, a second metal material layer, a mother integrated chip (IC), a son IC with a salient point, an insulation filling material, an adhering material, a lower filler and a plastic package material, wherein the lead frame comprises a chip carrier and a pin; the metal material layers are arranged on the upper surface and the lower surface of the lead frame; the insulation filling material is arranged under a step-type structure of the lead frame; the mother IC is arranged on the first metal material layer on the upper surface of the lead frame through an adhesive material; the son IC with the salient point is arranged on an active surface of the mother IC chip in a flip welding manner; the lower filler is arranged between the mother IC and the son IC with the salient point; and the plastic package material covers the mother IC, the son IC with the salient point, the adhesive material, the lower filler, a first metal lead wire and the lead frame. The invention provides a QFN (quad, flat and non-lead)-package-based three-dimensional package structure with high reliability, low cost and high input/output (I/O) density.
(ZH)
本发明公开了一种芯片上倒装芯片封装及制造方法。本封装包括引线框架、第一、第二金属材料层、母IC芯片、具有凸点的子IC芯片、绝缘填充材料、粘贴材料、下填料和塑封材料。引线框架包括芯片载体和引脚。金属材料层配置于引线框架上表面和下表面。绝缘填充材料配置于引线框架的台阶式结构下。母IC芯片通过粘贴材料配置于引线框架上表面的第一金属材料层位置,具有凸点的子IC芯片倒转焊接配置于母IC芯片的有缘面上。下填料配置于母IC芯片与具有凸点的子IC芯片之间。塑封材料包覆母IC芯片、具有凸点的子IC芯片、粘贴材料、下填料、第一金属导线和引线框架。本发明提供了基于QFN封装的高可靠性、低成本、高I/O密度的三维封装结构。