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1. CN102543937 - Flip chip on-chip package and manufacturing method thereof

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Office
China
Application Number 201110457533.9
Application Date 30.12.2011
Publication Number 102543937
Publication Date 04.07.2012
Grant Number
Grant Date 22.01.2014
Publication Kind B
IPC
H01L 23/498
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488consisting of soldered or bonded constructions
498Leads on insulating substrates
H01L 23/495
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488consisting of soldered or bonded constructions
495Lead-frames
H01L 23/31
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulation, e.g. encapsulating layers, coatings
31characterised by the arrangement
H01L 21/48
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/06-H01L21/326201
H01L 21/56
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56Encapsulations, e.g. encapsulating layers, coatings
H01L 21/50
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
CPC
H01L 21/4828
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
4814Conductive parts
4821Flat leads, e.g. lead frames with or without insulating supports
4828Etching
H01L 21/561
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
561Batch processing
H01L 23/3121
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulations, e.g. encapsulating layers, coatings, ; e.g. for protection
31characterised by the arrangement ; or shape
3107the device being completely enclosed
3121a substrate forming part of the encapsulation
H01L 23/49541
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; ; Selection of materials therefor
488consisting of soldered ; or bonded; constructions
495Lead-frames ; or other flat leads
49541Geometry of the lead-frame
H01L 23/49575
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; ; Selection of materials therefor
488consisting of soldered ; or bonded; constructions
495Lead-frames ; or other flat leads
49575Assemblies of semiconductor devices on lead frames
H01L 23/49582
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; ; Selection of materials therefor
488consisting of soldered ; or bonded; constructions
495Lead-frames ; or other flat leads
49579characterised by the materials of the lead frames or layers thereon
49582Metallic layers on lead frames
Applicants Beijing University of Technology
Inventors Qin Fei
Xia Guofeng
An Tong
Liu Chengyan
Wu Wei
Zhu Wenhui
Agents liu ping
Title
(EN) Flip chip on-chip package and manufacturing method thereof
(ZH) 一种芯片上倒装芯片封装及制造方法
front page image
Abstract
(EN) The invention discloses a flip chip on-chip package and a manufacturing method thereof. The flip chip on-chip package comprises a lead frame, a first metal material layer, a second metal material layer, a mother integrated chip (IC), a son IC with a salient point, an insulation filling material, an adhering material, a lower filler and a plastic package material, wherein the lead frame comprises a chip carrier and a pin; the metal material layers are arranged on the upper surface and the lower surface of the lead frame; the insulation filling material is arranged under a step-type structure of the lead frame; the mother IC is arranged on the first metal material layer on the upper surface of the lead frame through an adhesive material; the son IC with the salient point is arranged on an active surface of the mother IC chip in a flip welding manner; the lower filler is arranged between the mother IC and the son IC with the salient point; and the plastic package material covers the mother IC, the son IC with the salient point, the adhesive material, the lower filler, a first metal lead wire and the lead frame. The invention provides a QFN (quad, flat and non-lead)-package-based three-dimensional package structure with high reliability, low cost and high input/output (I/O) density.
(ZH)

本发明公开了一种芯片上倒装芯片封装及制造方法。本封装包括引线框架、第一、第二金属材料层、母IC芯片、具有凸点的子IC芯片、绝缘填充材料、粘贴材料、下填料和塑封材料。引线框架包括芯片载体和引脚。金属材料层配置于引线框架上表面和下表面。绝缘填充材料配置于引线框架的台阶式结构下。母IC芯片通过粘贴材料配置于引线框架上表面的第一金属材料层位置，具有凸点的子IC芯片倒转焊接配置于母IC芯片的有缘面上。下填料配置于母IC芯片与具有凸点的子IC芯片之间。塑封材料包覆母IC芯片、具有凸点的子IC芯片、粘贴材料、下填料、第一金属导线和引线框架。本发明提供了基于QFN封装的高可靠性、低成本、高I/O密度的三维封装结构。
Related patent documents
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