PATENTSCOPE will be unavailable a few hours for maintenance reason on Tuesday 19.11.2019 at 4:00 PM CET
Search International and National Patent Collections
Some content of this application is unavailable at the moment.
If this situation persists, please contact us atFeedback&Contact
1. (CN102265350) Random access memory architecture including midpoint reference

Office : China
Application Number: 200980152282.4 Application Date: 02.12.2009
Publication Number: 102265350 Publication Date: 30.11.2011
Publication Kind : A
Prior PCT appl.: Application Number:PCTUS2009066405 ; Publication Number:2010074904 Click to see the data
IPC:
G11C 11/00
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
CPC:
G11C 7/04
G11C 11/1655
G11C 11/1657
G11C 11/1659
G11C 11/1673
Applicants: Everspin Technologies Inc.
艾沃思宾技术公司
Inventors: Nahas Joseph J.
J·J·纳哈斯
Andre Thomas W.
T·W·安德
Subramanian Chitra K.
C·K·赛伯拉玛尼安
Agents: shen fazhen
中国国际贸易促进委员会专利商标事务所 11038
Priority Data: 12344339 26.12.2008 US
Title: (EN) Random access memory architecture including midpoint reference
(ZH) 包括中点基准的随机存取存储器架构
Abstract: front page image
(EN) A random access memory architecture includes a first series connected pair of memory elements (202, 206, 302, 306, 402, 404) having a first resistance and a second series connected pair of memory elements (204, 208, 304, 308, 406, 408) having a second resistance coupled in parallel with the first series connected pair of memory elements, wherein a current flows in the first direction through both of the first and second series connected pair of memory elements. A sense amplifier (14) is coupled to an array (16) of MRAM cells (77), each including a memory element, and includes a voltage bias portion (12), the voltage bias portion including the first and second series connected pair of memory elements. The memory elements may be, for example, magnetic tunnel junctions.
(ZH)

一种随机存取存储器架构包括具有第一电阻的第一对串联存储元件(202,206,302,306,402,404)和与第一对串联存储元件并联耦合的具有第二电阻的第二对串联存储元件(204,208,304,308,406,408),其中电流沿着第一方向流过第一和第二对串联存储元件两者。感测放大器(14)与每个都包括存储元件的MRAM单元(77)的阵列(16)耦合,并且包括电压偏置部分(12),该电压偏置部分包括第一和第二对串联存储元件。该存储元件可以是,例如,磁性隧道结。


Also published as:
KR1020110117111WO/2010/074904