Processing

Please wait...

Settings

Settings

Goto Application

1. CN101467265 - Self aligned gate jfet structure and method

Office China
Application Number 200780021526.6
Application Date 07.06.2007
Publication Number 101467265
Publication Date 24.06.2009
Publication Kind A
IPC
H01L 31/112
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
31Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength, or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
08in which radiation controls flow of current through the device, e.g. photoresistors
10characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
101Devices sensitive to infra-red, visible or ultra-violet radiation
112characterised by field-effect operation, e.g. junction field-effect photo- transistor
CPC
H01L 29/808
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
76Unipolar devices ; , e.g. field effect transistors
772Field effect transistors
80with field effect produced by a PN or other rectifying junction gate ; , i.e. potential-jump barrier
808with a PN junction gate ; , e.g. PN homojunction gate
H01L 29/1066
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
10with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
1066Gate region of field-effect devices with PN junction gate
H01L 29/41775
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
41characterised by their shape, relative sizes or dispositions
417carrying the current to be rectified, amplified or switched
41725Source or drain electrodes for field effect devices
41775characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
H01L 29/66901
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
66007Multistep manufacturing processes
66075of devices having semiconductor bodies comprising group 14 or group 13/15 materials
66227the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
66409Unipolar field-effect transistors
66893with a PN junction gate, i.e. JFET
66901with a PN homojunction gate
Applicants DSM Solutions Inc.
帝斯曼方案公司
Inventors Kapoor Ashok Kumar
阿首克·库马尔·卡泊尔
Agents xiao shanqiang nan ting
北京东方亿思知识产权代理有限责任公司
北京东方亿思知识产权代理有限责任公司
Priority Data 11450112 09.06.2006 US
Title
(EN) Self aligned gate jfet structure and method
(ZH) 自对准栅极结型场效应晶体管结构和方法
Abstract
(EN)
A JFET integrated onto a substrate having a semiconductor layer at least and having source and drain contacts over an active area and made of first polysilicon (or other conductors such as refractive metal or silicide) and a self-aligned gate contact made of second polysilicon which has been polished back to be flush with a top surface of a dielectric layer covering the tops of the source and drain contacts. The dielectric layer preferably has a nitride cap to act as a polish stop. In some embodiments, nitride covers the entire dielectric layer covering the source and drain contacts as well as the field oxide region defining an active area for said JFET. An embodiment with an epitaxially grown channel region formed on the surface of the substrate is also disclosed.

(ZH)

本发明公开了一种集成在衬底上的结型场效应晶体管(JFET),所述衬底至少具有半导体层,并且具有在有源区上的源触点和漏触点以及自对准栅极触点,其中所述源触点和漏触点由第一多晶硅(或其它导体,例如耐火金属或硅化物)制成,所述自对准栅极触点由第二多晶硅制成并被抛光以使其与覆盖源触点和漏触点顶部的电介质层的顶表面平齐。所述电介质层优选具有充当抛光阻挡层的氮化物帽层。在某些实施方式中,氮化物覆盖了覆盖源触点和漏触点的整个电介质层以及定义所述JFET的有源区的场氧化物区。本发明还公开了一种实施方式,其中外延生长沟道区形成在衬底表面上。