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1. CN101356511 - Power conservation via DRAM access

Office
China
Application Number 200680050850.6
Application Date 14.11.2006
Publication Number 101356511
Publication Date 28.01.2009
Grant Number 101356511
Grant Date 11.01.2012
Publication Kind B
IPC
G06F 12/08
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
CPC
Y02D 10/00
YSECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
10Energy efficient computing, e.g. low power processors, power management or thermal management
Applicants Montalvo Systems Inc.
太阳微系统有限公司
Inventors Moll Laurent R.
劳伦特·R·莫尔
Song Seungyoon Peter
先勇·皮特·宋
Glaskowsky Peter N.
皮特·N·格拉斯科斯奇
Cheng Yu-quin
程宇庆
Agents guo hongxi zhang jun
北京铭硕知识产权代理有限公司 11286
北京铭硕知识产权代理有限公司 11286
Priority Data 11351070 09.02.2006 US
11559133 13.11.2006 US
11559192 13.11.2006 US
60/736,632 15.11.2005 US
60/736,736 15.11.2005 US
60/761,220 23.01.2006 US
Title
(EN) Power conservation via DRAM access
(ZH) 通过DRAM存取的功率转换
Abstract
(EN)
Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges, or having specific characteristics of the accesses themselves, are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein.

(ZH)

由可选择性地在正常模式和缓冲器模式下操作的缓冲器/小型高速缓冲存储器来提供通过DRAM存取减少的功率转换。在缓冲器模式下(当CPU开始在低功率状态下操作时进入该缓冲器模式),与指定的物理地址范围相匹配或具有存取本身特定特性的(诸如由DMA装置产生的)非可高速缓冲存取被缓冲器/小型高速缓冲存储器处理,而不是被存储器控制器和DRAM处理。缓冲器/小型高速缓冲存储器处理包括:当引用失败时,分配行;当引用成功时,从缓冲器/小型高速缓冲存储器返回高速缓冲的数据。根据多个替换策略中的一个,在缓冲器/小型高速缓冲存储器中对行进行替换,所述多个替换策略包括:当没有可用的空闲行时,停止替换。在正常模式下(当CPU开始在高功率状态下操作时进入该正常模式),缓冲器/小型高速缓冲存储器与传统高速缓冲存储器类似地操作,并且在其中不处理非可高速缓冲存取。