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1. (CN101213747) Differential multiphase frequency divider

Office : China
Application Number: 200680023553.2 Application Date: 30.06.2006
Publication Number: 101213747 Publication Date: 02.07.2008
Publication Kind : A
Prior PCT appl.: Application Number:PCTIB2006052216 ; Publication Number:2007004182 Click to see the data
IPC:
H03K 5/15
H03K 23/54
H03K 3/356
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
5
Manipulating pulses not covered by one of the other main groups in this subclass
15
Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
23
Pulse counters comprising counting chains; Frequency dividers comprising counting chains
40
Gating or clocking signals applied to all stages, i.e. synchronous counters
50
using bi-stable regenerative trigger circuits
54
Ring counters, i.e. feedback shift register counters
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
3
Circuits for generating electric pulses; Monostable, bistable or multistable circuits
02
Generators characterised by the type of circuit or by the means used for producing pulses
353
by the use, as active elements, of field-effect transistors with internal or external positive feedback
356
Bistable circuits
CPC:
H03K 5/15093
H03K 23/425
Applicants: NXP BV
NXP股份有限公司
Inventors: Song Wenyi
W·宋
Agents: chenyuan zhangtian shu
北京天昊联合知识产权代理有限公司
北京天昊联合知识产权代理有限公司
Priority Data: 60/696,490 30.06.2005 US
Title: (EN) Differential multiphase frequency divider
(ZH) 差动多相分频器
Abstract: front page image
(EN) A multiphase divider comprises several differential latches connected in a ring. The number of latches in the ring is equal to the number of phases produced and the divisor applied to the input clock. The differential Q-outputs of one latch stage are connected to the corresponding differential D-inputs of the next latch stage. For even numbers of latch stages, the differential clock inputs of each are connected together and alternately to the divider clock input and its complement. The last differential Q-output is returned and cross- connected to the differential D-inputs of the first latch stage. For odd numbers of latch stages, the differential clock inputs of each are respectively connected in parallel to the divider clock input and its complement. The last differential Q-output is returned and straight-connected to the differential D-inputs of the first latch stage.
(ZH)

一种多相分频器包括以环路连接的多个差动锁存器。环路中锁存器的数目等于产生的相位的数目并等于加载在输入时钟上的分频比。一个锁存器级的差动Q输出端连接到下一个锁存器级的对应差动D输入端。对于偶数锁存器级,各级的差动时钟输入端连接在一起并且交替地连接到分频器时钟输入端及其互补输入端。最后的差动Q输出端返回并交叉连接到第一锁存器级的差动D输入端。对于奇数锁存器级,各级的差动时钟输入端并行地分别连接到分频器时钟输入端及其互补输入端。最后的差动Q输出端返回并直接连接到第一锁存器级的差动D输入端。


Also published as:
EP1900097JP2008545321US20090153201WO/2007/004182