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1. (CN101203831) Primitives to enhance line-level speculation

Office : China
Application Number: 200680022486.2 Application Date: 23.06.2006
Publication Number: 101203831 Publication Date: 18.06.2008
Grant Number: 101203831 Grant Date: 14.09.2011
Publication Kind : B
Prior PCT appl.: Application Number:PCTUS2006024727 ; Publication Number:2007002550 Click to see the data
IPC:
G06F 9/38
G06F 9/46
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
30
Arrangements for executing machine- instructions, e.g. instruction decode
38
Concurrent instruction execution, e.g. pipeline, look ahead
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
46
Multiprogramming arrangements
CPC:
G06F 9/526
G06F 9/30087
G06F 9/30101
G06F 9/3834
G06F 9/3842
G06F 9/3851
G06F 9/3861
Applicants: Intel Corp.
英特尔公司
Inventors: Jacobson Quinn
Q·雅克布森
Wang Hong
H·王
Shen John
J·舍恩
Chinya Gautham
G·金雅
Hammerlund Per
P·哈默伦德
Zou Xiang
X·邹
Bigbee Bryant
B·比格比
Kaushki Shivnandan
S·考舒基
Agents: wangyang
永新专利商标代理有限公司 72002
Priority Data: 11165639 23.06.2005 US
Title: (EN) Primitives to enhance line-level speculation
(ZH) 用于对存储器更新进行缓存的装置、方法和系统
Abstract: front page image
(EN) A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.
(ZH)

一种处理器可以包括地址监控表和原子更新表以支持推测线程。该处理器还可以包括一个或多个寄存器以保持与推测线程的执行相关的状态。该处理器可以支持一个或多个下列原语:将状态写入寄存器的指令,对提交所缓冲的存储器更新进行触发的指令,从状态寄存器读取状态的指令,和/或清除与陷阱/异常/中断处理相关联的状态位之一的指令。还描述和声明了其它实施例。


Also published as:
JP2009501366WO/2007/002550