(EN)
A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formed on the protective layer. The gate wire and the data wire include triple layers of an adhesion layer, a Ag containing layer and a protection layer. The adhesion layer includes one of Cr, Cr alloy, Ti, Ti alloy, Mo, Mo alloy, Ta, Ta alloy, the Ag containing layer includes Ag or Ag alloy, and the protection layer includes one of IZO, Mo, Mo alloy, Cr and Cr alloy.
(ZH) 本发明涉及一种薄膜晶体管阵列面板，包括：绝缘基片、形成于该绝缘基片上的栅极布线。栅极绝缘层覆盖该栅极布线。在该栅极绝缘层上形成半导体图案。在该栅极绝缘层和半导体图案上形成具有源极、漏极、和数据线的数据布线。在该数据布线上形成钝化层。在该钝化层上形成通过接触孔与漏极连接的像素电极。栅极布线和数据布线包括三层，即粘合层、含银层、以及钝化层。粘合层由Cr、Cr合金、Ti、Ti合金、Mo、Mo合金、Ta、Ta合金中的一种组成，含Ag层由Ag或Ag合金组成，而钝化层由IZO、Mo、Mo合金、Cr、及Cr合金中的一种组成。
