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1. CN1524269 - MTJ MRAM series-parallel architecture

Office
China
Application Number 01815003.9
Application Date 24.08.2001
Publication Number 1524269
Publication Date 25.08.2004
Grant Number 100565700
Grant Date 02.12.2009
Publication Kind C
IPC
G11C 11/16
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
02using magnetic elements
16using elements in which the storage effect is based on magnetic spin effect
CPC
G11C 11/15
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
02using magnetic elements
14using thin-film elements
15using multiple magnetic layers
H01L 27/228
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
22including components using galvano-magnetic effects, e.g. Hall effects; using similar magnetic field effects
222Magnetic non-volatile memory structures, e.g. MRAM
226comprising multi-terminal components, e.g. transistors
228of the field-effect transistor type
Applicants Motorola Inc
艾沃思宾技术公司
Inventors Durlam Mark
彼得·K·纳吉
Deherrera Mark
马克·德和雷拉
Naji Peter K.
马克·杜尔拉姆
Agents li deshan
中国国际贸易促进委员会专利商标事务所
Priority Data 09649117 28.08.2000 US
Title
(EN) MTJ MRAM series-parallel architecture
(ZH) 磁隧道结随机访问存储器系统
Abstract
(EN)
Magnetic tunnel junction random access memory architecture in which an array of memory cells (18) is arranged in rows and columns (15) and each memory cell includes a magnetic tunnel junction (20, 22, 24, 26) and a control transistor (21, 23, 25, 27) connected in parallel. A control line (WL) is connected to the gate of each control transistor in a row of control transistors and a metal programming line (36-39) extending adjacent to each magnetic tunnel junction is connected to the control line in spaced apart intervals by vias. Further, groups (16, 17) of memory cells in each column are connected in series to form local bit lines which are connected in parallel to global bit lines (19). The series-parallel configuration is read using a centrally located column to provide a reference signal and data from columns on each side of the reference column is compared to the reference signal or two columns in proximity are differentially compared.

(ZH)

一种磁隧道结随机访问存储器体系结构,其中存储器单元阵列(18)按行和列(15)排列,各个存储器单元包含并联的磁隧道结(20、22、24、26)和控制晶体管(21、23、25、27)。控制线(WL)被连接到控制晶体管行中各个控制晶体管的栅极,延伸以邻近各个磁隧道结的金属编程线路(36-39)通过通孔按照分离开的间隔被连接到控制线。此外,各个列中的存储器单元组(16、17)串联以形成局部位线,局部位线并联到全局位线(19)。通过使用中央定位的列提供基准信号,读取串并行结构,并且将来自基准列的各侧上的列的数据与基准信号相比较,或者差动比较接近的2个列。