Processing

Please wait...

Settings

Settings

Goto Application

1. CN1155341 - Flash memory based main memory

Office China
Application Number 95193421.X
Application Date 01.06.1995
Publication Number 1155341
Publication Date 23.07.1997
Grant Number 1102772
Grant Date 05.03.2003
Publication Kind C
IPC
G06F 12/08
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
CPC
G06F 12/0607
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
0607Interleaved addressing
G06F 12/08
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
G06F 2212/2022
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
20Employing a main memory using a specific memory technology
202Non-volatile memory
2022Flash memory
G11C 7/1045
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1015Read-write modes for single port memories, i.e. having either a random port or a serial port
1045Read-write mode select circuits
G11C 7/1072
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1072for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
Y02D 10/00
YSECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
10Energy efficient computing, e.g. low power processors, power management or thermal management
Applicants Intel Co.
英特尔公司
Inventors D. R. Mills
D·R·米尔斯
B. L. Dipert
B·L·迪佩特
S. sambandan
S·森班丹
B·麦科米克
R·D·帕什利
Agents MA TIELIANG
中国专利代理(香港)有限公司
中国专利代理(香港)有限公司
Priority Data 08253499 03.06.1994 US
Title
(EN) Flash memory based main memory
(ZH) 基于快速存储器的主存储器
Abstract
(EN)
A flash memory chip that can be switched into four different read modes is described. And computer system employing same is also discribed. In asynchronous flash mode, the flash memory is read as a standard flash memory. In synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock period. The data stored at the specified addresses are output sequentially during subsequent clock periods. In asynchronous DRAM mode, the flash memory emulates DRAM. In synchronous DRAM mode the flash memory emulates synchronous DRAM.

(ZH)

描述了可被切换至4种不同的读出方式的快速存储器芯片(320)。还描述了利用了这些方式的计算机系统(100、200、300、800、1300、1500)和体系。在第一种读出方式即异步快速方式中,快速存储器(130)被作为标准快速存储器读出。在第二种方式即同步快速方式中,向快速存储器芯片(320)提供时钟信号和每时钟信号一个地址地指定属于一数据串的一系列地址。在第三种方式即异步DRAM(动态随机存取存储器)方式中,快速存储器(130)模拟DRAM。在第四种读出方式即同步DRAM方式中,组合第二和第三种方式的特点,得到模拟同步DRAM的快速存储器。