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1. CN113039532 - SYSTEM FOR IMPLEMENTING SHARED LOCK FREE MEMORY IMPLEMENTING COMPOSITE ASSIGNMENT

Office
China
Application Number 201980063918.1
Application Date 24.07.2019
Publication Number 113039532
Publication Date 25.06.2021
Publication Kind A
IPC
G06F 13/16
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
H01L 27/108
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
G11C 13/00
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
13Digital stores characterised by the use of storage elements not covered by groups G11C11/, G11C23/, or G11C25/173
CPC
G11C 7/1006
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
G11C 11/4096
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write [R-W] circuits 
4096Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
G11C 7/1012
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
1012Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
G11C 11/4093
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write [R-W] circuits 
4093Input/output [I/O] data interface arrangements, e.g. data buffers
G11C 11/4076
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
4076Timing circuits
H01L 27/10897
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
10897Peripheral structures
Applicants JERUSALEM COLLEGE OF TECHNOLOGY
耶路撒冷理工学院
Inventors MIZRAHI SHIMON
希蒙·米兹拉希
YEHEZKAEL RAPHAEL BERAKHAEL
拉斐尔·贝拉克哈尔·耶海兹卡尔
ATTIA RUBEN
鲁本·阿蒂亚
LAX EREZ
埃雷斯·拉克斯
BERLOWITZ DEVORA
德沃拉·贝洛维茨
GOLDSTEIN MOSHE
摩西·戈德斯坦
DAYAN DAVID
戴维·达扬
Agents 北京康信知识产权代理有限责任公司 11240
Priority Data 62/702,373 24.07.2018 US
Title
(EN) SYSTEM FOR IMPLEMENTING SHARED LOCK FREE MEMORY IMPLEMENTING COMPOSITE ASSIGNMENT
(ZH) 用于实现实施复合赋值的共享无锁存储器的系统
Abstract
(EN) It is an object of the disclosed technique to provide a novel method and system for shared concurrent access to a memory cell. In accordance with the disclosed technique, there is thus provided a system for shared concurrent access to a memory cell, which includes at least one shared memory cell, an evaluator and a plurality of processing agents coupled to the input of the evaluator. The evaluator is further coupled with at least one memory cell. The evaluator is configured to evaluate an expression for performing multiple concurrent composite assignments on at least one shared memory cell. The evaluator further allows each of the plurality of processing agents to perform concurrent composite assignments on at least one shared memory cell. The composite assignments do not include a read operation of at least one shared memory cell by the plurality of processing agents.
(ZH) 所公开的技术的目的是提供用于对存储单元共享并发访问的新颖方法和系统。根据所公开的技术,因此提供了一种对存储单元共享并发访问的系统,该系统包括至少一个共享存储单元、估计器和耦接到估计器的输入端的多个处理代理。估计器还与至少一个存储单元耦接。估计器被配置为估计用于对至少一个共享存储单元执行多个并发复合赋值的表达式。估计器还允许多个处理代理中的每个处理代理对至少一个共享存储单元执行并发复合赋值。复合赋值不包括多个处理代理对至少一个共享存储单元的读取操作。
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