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1. CN110235408 - CLOCK DATA RECOVERY WITH NON-UNIFORM CLOCK TRACKING

Office
China
Application Number 201880009235.3
Application Date 12.01.2018
Publication Number 110235408
Publication Date 13.09.2019
Grant Number 110235408
Grant Date 06.08.2021
Publication Kind B
IPC
H04L 7/00
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7Arrangements for synchronising receiver with transmitter
H03L 7/081
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7Automatic control of frequency or phase; Synchronisation
06using a reference signal applied to a frequency- or phase-locked loop
08Details of the phase-locked loop
081provided with an additional controlled phase shifter
H04L 7/033
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7Arrangements for synchronising receiver with transmitter
02Speed or phase control by the received code signals, the signals containing no special synchronisation information
033using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
CPC
H04L 7/0025
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7Arrangements for synchronising receiver with transmitter
0016correction of synchronization errors
002correction by interpolation
0025interpolation of clock signal
H04L 7/0337
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7Arrangements for synchronising receiver with transmitter
02Speed or phase control by the received code signals, the signals containing no special synchronisation information
033using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
0337Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
H03L 2207/50
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
2207Indexing scheme relating to automatic control of frequency or phase and to synchronisation
50All digital phase-locked loop
H04L 25/03273
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
25Baseband systems
02Details
03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
03006Arrangements for removing intersymbol interference
03178Arrangements involving sequence estimation techniques
03248Arrangements for operating in conjunction with other apparatus
03273with carrier recovery circuitry
H04L 43/16
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
43Arrangements for monitoring or testing packet switching networks
16using threshold monitoring
H04L 2027/0069
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
27Modulated-carrier systems
0014Carrier regulation
0044Control loops for carrier regulation
0063Elements of loops
0069Loop filters
Applicants QUALCOMM INC.
高通股份有限公司
Inventors SONG YU
宋宇
ZHU ZHI
朱志
LI MIAO
李淼
SUN LI
孙立
SONG DEQIANG
宋德强
CHANG CHIA-HENG
C·H·常
Agents 北京市金杜律师事务所 11256
Priority Data 15422050 01.02.2017 US
Title
(EN) CLOCK DATA RECOVERY WITH NON-UNIFORM CLOCK TRACKING
(ZH) 具有非均匀时钟跟踪的时钟数据恢复
Abstract
(EN) Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).
(ZH) 根据本公开的方面,描述了用于调整时钟数据恢复(CDR)电路的相位步长的系统和方法。在某些方面,一种用于调整CDR电路的相位步长的方法包括:感测CDR电路的频率偏移,以及基于所感测的频率偏移来调整CDR电路的相位步长。可以通过感测CDR电路的环路滤波器的积分路径上的信号水平来感测频率偏移。可以通过使用调制器(例如,sigma‑delta调制器)在第一相位步长和第二相位步长之间切换CDR电路来调整CDR电路的相位步长。