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1. CN110114874 - INTERCONNECT STRUCTURE FOR STACKED DIE IN A MICROELECTRONIC DEVICE

Office
China
Application Number 201680091284.7
Application Date 30.12.2016
Publication Number 110114874
Publication Date 09.08.2019
Publication Kind A
IPC
H01L 25/065
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04the devices not having separate containers
065the devices being of a type provided for in group H01L27/78
H01L 23/498
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488consisting of soldered or bonded constructions
498Leads on insulating substrates
H01L 23/525
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
525with adaptable interconnections
H01L 25/00
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
CPC
H01L 23/49816
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; ; Selection of materials therefor
488consisting of soldered ; or bonded; constructions
498Leads, ; i.e. metallisations or lead-frames; on insulating substrates, ; e.g. chip carriers
49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
H01L 23/49822
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; ; Selection of materials therefor
488consisting of soldered ; or bonded; constructions
498Leads, ; i.e. metallisations or lead-frames; on insulating substrates, ; e.g. chip carriers
49822Multilayer substrates
H01L 23/5389
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
538the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
5389the chips being integrally enclosed by the interconnect and support structures
H01L 24/19
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
24Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
18High density interconnect [HDI] connectors; Manufacturing methods related thereto
19Manufacturing methods of high density interconnect preforms
H01L 24/20
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
24Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
18High density interconnect [HDI] connectors; Manufacturing methods related thereto
20Structure, shape, material or disposition of high density interconnect preforms
H01L 24/32
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
24Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
31Structure, shape, material or disposition of the layer connectors after the connecting process
32of an individual layer connector
Applicants INTEL IP CORP
英特尔IP公司
Inventors WAGNER THOMAS
T.瓦纳
WOLTER ANDREAS
A.沃尔特
SEIDEMANN GEORG
G.塞德曼
Agents 中国专利代理(香港)有限公司 72001
中国专利代理(香港)有限公司 72001
Title
(EN) INTERCONNECT STRUCTURE FOR STACKED DIE IN A MICROELECTRONIC DEVICE
(ZH) 微电子设备中堆叠管芯的互连结构
Abstract
(EN)
A microelectronic package includes at least two semiconductor die, one die stacked over at least partially another. At least the upper die is oriented with its active surface facing in the direction of a redistribution structure, and one or more wires are coupled to extend from contacts on that active surface into conductive structures in the redistribution structure.

(ZH)
微电子封装包括至少两个半导体管芯,一个管芯至少部分堆叠在另一个上。至少上层管芯定向成它的有效表面面向重分布结构的方向,并且将一个或多个线耦合以从该有效表面上的触点延伸到重分布结构中的导电结构中。