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1. CN108735664 - Fabrication method of amorphous silicon TFT substrate

Office
China
Application Number 201810488941.2
Application Date 21.05.2018
Publication Number 108735664
Publication Date 02.11.2018
Publication Kind A
IPC
H01L 21/77
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
H01L 21/336
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334Multistep processes for the manufacture of devices of the unipolar type
335Field-effect transistors
336with an insulated gate
CPC
H01L 27/1288
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12the substrate being other than a semiconductor body, e.g. an insulating body
1214comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
1259Multistep manufacturing methods
1288employing particular masking sequences or specially adapted masks, e.g. half-tone mask
H01L 29/66757
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
66007Multistep manufacturing processes
66075of devices having semiconductor bodies comprising group 14 or group 13/15 materials
66227the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
66409Unipolar field-effect transistors
66477with an insulated gate, i.e. MISFET
66742Thin film unipolar transistors
6675Amorphous silicon or polysilicon transistors
66757Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
Applicants WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
武汉华星光电技术有限公司
Inventors LIU GUANGHUI
刘广辉
Agents 深圳市德力知识产权代理事务所 44265
深圳市德力知识产权代理事务所 44265
Title
(EN) Fabrication method of amorphous silicon TFT substrate
(ZH) 非晶硅TFT基板的制作方法
Abstract
(EN) The invention provides a fabrication method of an amorphous silicon TFT substrate. The fabrication method comprises the steps of firstly, forming a first photoresist layer with photoresist patterns having three thicknesses by a first-time exposure process, and completing patterning of four layers, namely an amorphous layer, an N-type doping amorphous layer, a first transparent conductive layer anda source-drain metal layer by the first photoresist layer and by an etching process for three times and an ashing process for two times; secondly, patterning a passivation layer by a second-time exposure process; and finally, forming a second photoresist layer with photoresist patterns having two thicknesses by a third-time exposure process, and completing patterning of two layers, namely a second transparent conductive layer and a gate metal layer by the second photoresist layer and by the etching process for two times and the ashing process for one time. Compared with a traditional 4mask process, the optimization process has the advantages that an optical mask process for one time is omitted, a 3mask process of the amorphous silicon TFT substrate is achieved, so that the integral yieldof a factory can be improved, and the cost is reduced.
(ZH) 本发明提供一种非晶硅TFT基板的制作方法,首先经第一道曝光制程形成具有三个厚度的光阻图案的第一光阻层,并通过三次蚀刻制程和两次灰化制程,利用第一光阻层完成非晶硅层、N型掺杂非晶硅层、第一透明导电层及源漏极金属层这四层的图案化,然后经第二道曝光制程进行钝化层的图案化,最后经第三道曝光制程形成具有两个厚度的光阻图案的第二光阻层,通过两次蚀刻制程和一次灰化制程,利用第二光阻层完成第二透明导电层及栅极金属层这两层的图案化,本发明通过优化工艺,相对于现有4mask工艺进一步节省了一道光罩制程,实现非晶硅TFT基板的3mask制作工艺,从而可以提升工厂的整体产能,降低成本。
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