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1. (CN108351378) SYSTEMS AND METHODS OF TESTING MULTIPLE DIES

Office : China
Application Number: 201680065275.0 Application Date: 01.12.2016
Publication Number: 108351378 Publication Date: 31.07.2018
Publication Kind : A
Prior PCT appl.: Application Number:PCTUS2016064412 ; Publication Number: Click to see the data
IPC:
G01R 31/28
H01L 21/301
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28
Testing of electronic circuits, e.g. by signal tracer
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
301
to subdivide a semiconductor body into separate parts, e.g. making partitions
Applicants: TEXAS INSTRUMENTS INC
德州仪器公司
Inventors: PAREKHJI RUBIN AJIT
鲁宾·阿吉特·佩尔科治
MEHENDALE MAHESH M
马赫什·M·梅亨达勒
MENEZES VINOD
维诺德·梅内塞斯
SINGHAL VIPUL K
维普·K·辛哈尔
Agents: 北京律盟知识产权代理有限责任公司 11287
Priority Data: 6457/CHE/2015 01.12.2015 IN
15/130,429 15.04.2016 US
Title: (EN) SYSTEMS AND METHODS OF TESTING MULTIPLE DIES
(ZH) 测试多个裸片的系统及方法
Abstract: front page image
(EN) In described examples of a method (800) of testing a semiconductor wafer including a scribe line and multiple dies, the method (800) includes implementing a first landing pad on the scribe line (802),and implementing a first interconnect on the scribe line and between the first landing pad and a first cluster of the plurality of dies (804), thereby coupling the first landing pad to the first cluster of dies. The method (800) further includes performing the testing of the first cluster of dies using automated test equipment (ATE) coupled to a probe tip by contacting the first landing pad withthe probe tip and applying an ATE resource to the first cluster of dies (806).
(ZH) 在测试包含划线及多个裸片的半导体晶片的方法(800)的所描述实例中,所述方法(800)包含:在所述划线上实施第一着陆垫(802);及在所述划线上且在所述第一着陆垫与所述多个裸片的第一集群之间实施第一互连件(804),借此将所述第一着陆垫耦合到所述第一裸片集群。所述方法(800)进一步包含使用耦合到探针尖端的自动化测试设备ATE通过使所述第一着陆垫接所述触探针尖端并将ATE资源应用到所述第一裸片集群执行所述第一裸片集群的测试(806)。
Also published as:
WO/2017/096038