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1. CN107910309 - Isolating pad and chip comprising same

Office
China
Application Number 201711289369.9
Application Date 07.12.2017
Publication Number 107910309
Publication Date 13.04.2018
Publication Kind A
IPC
H01L 23/488
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488consisting of soldered or bonded constructions
H01L 23/485
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
482consisting of lead-in layers inseparably applied to the semiconductor body
485consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H01L 23/498
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488consisting of soldered or bonded constructions
498Leads on insulating substrates
CPC
H01L 2224/05
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
H01L 2224/48463
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
484Connecting portions
48463the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
H01L 23/488
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; ; Selection of materials therefor
488consisting of soldered ; or bonded; constructions
H01L 23/485
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; ; Selection of materials therefor
482consisting of lead-in layers inseparably applied to the semiconductor body
485consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H01L 23/49838
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; ; Selection of materials therefor
488consisting of soldered ; or bonded; constructions
498Leads, ; i.e. metallisations or lead-frames; on insulating substrates, ; e.g. chip carriers
49838Geometry or layout
Applicants 2PAI SEMICONDUCTOR CO., LIMITED
荣湃半导体(上海)有限公司
Inventors DONG ZHIWEI
董志伟
Agents 北京市中伦律师事务所 11410
Title
(EN) Isolating pad and chip comprising same
(ZH) 一种隔离式焊盘以及包括该焊盘的芯片
Abstract
(EN) The invention provides an isolating pad, which comprises a first conductive region, a second conductive region, an insulating layer and an insulating isolation area, wherein the insulating layer is arranged on the first conductive region and an opening is formed, so that one part of the first conductive region and the second conductive region are exposed; the insulating isolation area is arrangedbetween the second conductive region and the first conductive region; and when the opening is filled with a conductive material, the first conductive region is electrically connected with the second conductive region. According to the isolating pad, the chip area required for wiring can be reduced, the testing and starting time is shortened, use of noble metals, such as a gold wire and a copper wire is reduced, and programming can be conveniently carried out, thereby greatly reducing the cost of a chip.
(ZH) 本发明提供一种隔离式焊盘,包括:第一导电区,第二导电区,绝缘层和绝缘隔离区,其中,所述绝缘层设置在所述第一导电区上并形成开口,使得所述第一导电区的一部分和第二导电区暴露;所述第二导电区与所述第一导电区之间设置有所述绝缘隔离区;当所述开口处被填充导电材料时,所述第一导电区和第二导电区电连接。本发明所提供的技术方案能够降低布线所需的芯片面积,降低测试和启动时间,减少贵重金属,例如金线和铜线的使用,并且能够方便地进行编程,从而较大地降低了芯片的成本。