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1. CN106133902 - FACE-UP SUBSTRATE INTEGRATION WITH SOLDER BALL CONNECTION IN SEMICONDUCTOR PACKAGE

Office
China
Application Number 201580014299.9
Application Date 11.03.2015
Publication Number 106133902
Publication Date 16.11.2016
Grant Number 106133902
Grant Date 31.08.2018
Publication Kind B
IPC
H01L 23/48
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/538
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
538the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/64
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
58Structural electrical arrangements for semiconductor devices not otherwise provided for
64Impedance arrangements
H05K 1/02
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
02Details
H05K 1/03
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
02Details
03Use of materials for the substrate
H05K 1/11
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
02Details
11Printed elements for providing electric connections to or between printed circuits
CPC
H01L 23/48
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; ; Selection of materials therefor
H01L 23/5385
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
538the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
5385Assembly of a plurality of insulating substrates
H01L 23/645
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
58Structural electrical arrangements for semiconductor devices not otherwise provided for ; , e.g. in combination with batteries
64Impedance arrangements
645Inductive arrangements
H01L 2924/00
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
H01L 2924/0002
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
0001Technical content checked by a classifier
0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
H01L 2924/19101
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
191Disposition
19101of discrete passive components
Applicants QUALCOMM INCORPORATED
高通股份有限公司
Inventors KIM DAEIK DANIEL
D·D·金
KIM JONGHAE
J·金
ZUO CHENGJIE
C·左
YUN CHANGHAN HOBIE
C·H·尹
VELEZ MARIO FRANCISCO
M·F·维纶茨
MIKULKA ROBERT PAUL
R·P·米库尔卡
Agents 上海专利商标事务所有限公司 31100
Priority Data 14220913 20.03.2014 US
Title
(EN) FACE-UP SUBSTRATE INTEGRATION WITH SOLDER BALL CONNECTION IN SEMICONDUCTOR PACKAGE
(ZH) 半导体封装中具有焊球连接的正面朝上基板集成
Abstract
(EN) The invention discloses a face-up substrate integration with a solder ball connection in a semiconductor package. According to the invention, systems and methods relate to a semiconductor package 200 comprising a first substrate or a 2D passive-on-glass (POG) structure with a passive component 204 and a first set of one or more package pads 203 formed on a face of a glass substrate 202. The semiconductor package also includes a second or laminate substrate 207 with a second set of one or more package pads 205 formed on a face of the second or laminate substrate. Solder balls 206 are dropped, configured to contact the first set of one or more package pads with the second set of one or more package pads, wherein the first substrate or the 2D POG structure is placed face-up on the face of the second or laminate substrate. A printed circuit board (PCB) 208 can be coupled to a bottom side of the second or laminate substrate.
(ZH) 半导体封装中具有焊球连接的正面朝上基板集成。系统和方法涉及半导体封装200,其包括第一基板或具有形成在玻璃基板202的正面上的无源组件204以及第一组一个或多个封装焊盘203的2D玻璃上无源器件(POG)结构。该半导体封装还包括第二或层压基板207,其具有形成在第二或层压基板的正面上的第二组一个或多个封装焊盘205。焊球206被滴落、配置成使第一组一个或多个封装焊盘与第二组一个或多个封装焊盘接触,其中第一基板或2D POG结构被正面朝上置于第二或层压基板的正面上。印刷电路板(PCB)208可耦合至第二或层压基板的底侧。
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BR112016021591This application is not viewable in PATENTSCOPE because the national phase entry has not been published yet or the national entry is issued from a country that does not share data with WIPO or there is a formatting issue or an unavailability of the application.