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1. (US20120215972) Logical address offset in response to detecting a memory formatting operation
Office : United States of America
Application Number: 13459923 Application Date: 30.04.2012
Publication Number: 20120215972 Publication Date: 23.08.2012
Grant Number: 08683173 Grant Date: 25.03.2014
Publication Kind : B2
IPC:
G06F 12/10
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
02
Addressing or allocation; Relocation
08
in hierarchically structured memory systems, e.g. virtual memory systems
10
Address translation
CPC:
G06F 12/06
G06F 3/0608
G06F 3/0638
G06F 3/0679
G06F 12/0246
G06F 2212/7202
Applicants: Asnaashari Mehdi
Micron Technology, Inc.
Benson William E.
Inventors: Asnaashari Mehdi
Benson William E.
Agents: Brooks, Cameron & Huebsch, PLLC
Priority Data:
Title: (EN) Logical address offset in response to detecting a memory formatting operation
Abstract: front page image
(EN)

The present disclosure includes methods, devices, and systems for a logical address offset. One method embodiment includes detecting a memory unit formatting operation. Subsequently, in response to detecting the formatting operation, the method includes inspecting format information on the memory unit, calculating a logical address offset, and applying the offset to a host logical address.