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1. WO2010125164 - THROUGH SUBSTRATE VIAS

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[ EN ]AMENDEDinitial

AMENDED CLAIMS received by the International Bureau on 06 JULY 2010

1. A method for forming a via in a portion of a semiconductor wafer comprising a substrate, the method comprising the steps of: forming a trench surrounding a first part of the substrate such that the first part is separated from a second part of the substrate, wherein the trench extends through the substrate; forming a hole through the substrate within the first part; and forming a first metal within the hole, wherein the first metal extends from a front surface of the substrate to a back surface of the substrate, and wherein the via comprises the hole and the first metal; further comprising the step of: forming a second metal within the trench, wherein the forming of the first metal and the forming of the second metal comprise: forming metal plating at least within the hole and the trench; etching the metal plating, wherein, after the etching, the metal plating is discontinuous from an outside interior wall of the trench to an inside interior wall of the trench; and removing of any of the metal plating that was formed on the back surface of the substrate.

2. The method of claim 1 further comprising the step of: forming at least one of a first dielectric within the trench, and a second dielectric within the hole, wherein the first dielectric comprises at least one of a first layer and a second layer, wherein the first layer comprises a low-temperature oxide, and wherein at least one of the second layer and the second dielectric comprise at least one of silicon-dioxide, oxide, polyimide, underfill, resist, an organic insulator, low temperature co-fired ceramic paste, and a void.

3. The method of claim 1 further comprising the steps of: forming an insulating layer on the back surface of the portion of the semiconductor wafer; and forming at least one of a back contact within the insulating layer, and a pad upon the insulating layer, wherein the at least one of the back contact and the pad is coupled to the via.

4. The method of claim 1 further comprising the step of: forming a dielectric layer over at least a portion of the metal plating that is within the hole prior to etching the metal plating.

5. The method of claim 1, wherein the forming of the metal plating comprises forming a liner at least within the hole and the trench, forming a seed layer at least within the hole and the trench, and electro-plating, wherein the etching of the metal plating comprises etching of the seed layer, and etching of the liner, wherein, after the etching of the metal plating, the seed layer and the liner are discontinuous from the outside interior wall of the trench to the inside interior wall of the trench, and wherein the removing of the any of the metal plating that was formed on the back surface of the substrate comprises removing of any of the seed layer and liner that was formed on the back surface of the substrate.

6. The method of claim 1 , wherein the etching of the metal plating comprises: a first electro-etching operation that removes at least a portion of the metal plating adjacent to at least a portion of a bottom surface of the trench; a reactive-ion etching operation that removes at least that portion of a seed layer adjacent to the at least a portion of the bottom surface of the trench, and electrically decouples the first metal from that portion of the second metal formed on the outside interior wall of the trench; and a second electro-etching operation that removes at least the portion of the second metal formed on the outside interior wall of the trench.

7. The method of claim 1, further comprising forming a dielectric on the sidewall of the first part of the substrate exposed within the trench, wherein the hole, formed after the forming of the dielectric, abuts the dielectric.

8. The method of claim 1 , wherein the portion of the semiconductor wafer further comprises a front surface layer formed upon the front surface of the substrate, wherein the forming of the trench, the forming of the hole and the forming of the first metal are performed after the front surface layer has been formed, and wherein the forming of the hole and the forming of the trench comprise etching into the substrate through the back surface of the substrate.

9. The method of claim 8, wherein the front surface layer comprises a front contact, and wherein the via is coupled to the front contact.

10. The method of claim 1, wherein the portion of the semiconductor wafer comprises a portion of a thinned semiconductor wafer, and wherein the forming of the trench, the forming of the hole and the forming of the first metal are performed after the portion of the semiconductor wafer has been thinned.

11. The method of claim 1 , wherein the forming of the first metal comprises electro-plating metal on the walls of the hole after forming a first dielectric within the trench.

12. The method of claim 1 , wherein the forming of at least one of the hole and the trench comprises at least one of reactive-ion etching, deep reactive-ion etching, and wet etching.

13. The method of claim 1, wherein the first part is electrically decoupled from the second part.

14. The method of claim 13, wherein the trench extends through an electrically conducting portion of the substrate, and wherein at least one of: i) the trench stops on an electrically insulating layer, and ii) the trench stops within the electrically insulating layer.

15. The method of claim 14, wherein at least one of: i) a front surface layer and ii) a trench extension of the front surface layer comprises the electrically insulating layer, and wherein the electrically insulating layer is adapted to at least partially control an etched depth of the trench.

16. The method of claim 1, wherein at least one of: i) the forming of the first metal comprises electro-plating, and ii) the first metal comprises copper.

17. The method of claim 1, wherein the trench comprises an annulus, and wherein the hole comprises a cylinder.