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1. WO2021060989 - SYSTEM AND BIO-IMPLANTABLE CHIP FOR MEASURING ELECTRICAL RESISTANCE FOR INTEGRITY MONITORING, AND MANUFACTURING METHOD

Note: Text based on automatic Optical Character Recognition processes. Please use the PDF version for legal matters

[ EN ]

Title:

SYSTEM AND BIO-IMPLANTABLE CHIP FOR MEASURING ELECTRICAL RESISTANCE FOR INTEGRITY MONITORING, AND MANUFACTURING METHOD

Description

The present invention relates generally to a system, a sensor, a manufacturing method and a bio-implantable chip for measuring electrical resistance for integrity monitoring of bio-implantable chips.

BACKGROUND OF THE INVENTION

Implantable devices are a type of medical implants which consist of electronics and suitable for partly but mostly total introduction in the human body with the intention to remain there for a certain period of time and at least beyond the procedure of implanting the device. Implantable devices may be classified as active and passive device of which the active devices contain electronics which are powered by some power source.

One of the major challenges in active implantable devices is the search for smaller, more robust housings which are less likely to be repelled by the human body and which have a shape and made from a material which resembles bodily materials. Typically, housings are made from titanium, which is robust and reliable. Titanium housings are however also heavy, stiff and not very suitable for bodily like shapes. In the search for alternative materials, titanium housings are more and more replaced by flexible polymers and thin-film coating layers. These are more suitable to manufacture small housings and unconventional shapes which are typically required for certain applications like brain or nerve implants.

Once implanted, the active implantable devices need to resist the wet ionic environments of the human body. In the human body water molecule and ion ingress can take place which may find its way through the housing or the additional protective layer. The housing or layers will degrade and this will reduce the level of protection to the internal components. This may cause shorts and/or hard opens in the electronic circuits in the housing and to the integrated components which will eventually result in failure of the device.

When the housing and/or its additional protective layer degrades, the electrical resistance drops. Measuring electrical resistance is therefore considered a reliable way of monitoring integrity of active implantable devices.

Known methods for testing integrity of the active implantable devices are considered not efficient and not effective since they fail to signal early degradation, they are based on a simple single thresholded mechanism which aren’t able to provide the level of failure but simply indicate a pass/fail in view of the threshold, moreover, known methods fail to provide insight in the failure mechanism of the device or reveal the path ways for water and ion propagation through the integrated circuits.

In view of the search for alternatives for titanium as a material for manufacturing the housing of active implantable devices, there is a need to gain more insight in the robustness of these alternative materials. Accordingly, there is a need for an improved method of measuring of electrical resistance of the housing and/or protective layer on the housing of a bio-implantable chip.

SUMMARY

It is an object of the present invention, to provide an improved method of and system for measuring of electrical resistance.

It is a further object of the present invention, to provide an improved method of and system for measuring of electrical resistance which is capable to measure at very high range, e.g. peta-ohm, electrical resistance with a high level of accuracy.

In a first aspect, there is provided, a resistance measurement system for measuring electrical resistance for integrity monitoring of bio-implantable chips, said resistance measurement system comprising:

a sensor element comprising:

a node, comprising a stack of successive electrically conductive layers, said stack comprising a layer which comprises a charge holding capacitor arranged for pre-charging said capacitor to a predetermined voltage level, and a plurality of sensing layers, wherein each of said sensing layers being mutually electrically isolated from each other;

a switching unit arranged for connecting and disconnecting said charge holding capacitor of said node with a power supply; and

a voltage sensor arranged for determining a voltage level of said node; and said resistance measurement system further comprising:

a control unit, arranged for controlling said switching unit to switch said node between a first state in which said charge holding capacitor of said node is charged to a predetermined voltage level, and a second state in which said node is floating once said predetermined voltage level has been reached, and wherein said control unit is further arranged for determining a discharge time, wherein said discharge time is derived from counting clock pulses between switching said node from said first to said second state and said voltage sensor determining said node to drop below a predetermined discharge voltage level;

a calculation unit for calculating said electrical resistance of said chip, wherein said electrical resistance change is calculated as proportion between a said discharge time and a reference discharge time having a known reference electrical resistance.

Resistance measurement systems may be used in a wide variety of applications such as multi-modal lab-on-chip applications, DNA sequencing, bio compatible polymer encapsulation research, electronic security monitoring for tampering, and radiation-hardening/monitoring of chips. Also, in the field of active implantable devices such resistance measurement systems are very suitable for chip integrity monitoring of such microchips in wet environments.

In the area of active implantable chips special materials are typically used to protect the components of the chips. These special materials are conventionally metallic materials such as titanium since it is considered one of the most biocompatible metals due to the resistance to corrosion from the bodily fluids, bio-inertness, capacity for osseointegration, and high fatigue limit. The ability of titanium to withstand the harsh wet environments is a result of the protective oxide film that is naturally formed in the presence of oxygen. The oxide film is strongly adhered, insoluble, and chemically impermeable, such that reactions between the metal and the surrounding wet bodily environment is prevented.

Titanium is therefore a highly suitable material for manufacturing housings of active and passive implantable devices. Manufacturing housings of implantable devices from titanium also has disadvantages since they are typically heavy, stiff and not very suitable for bodily like shapes. In the search for alternative materials, titanium housings are more and more replaced by flexible polymers and thin-film coating layers. These are more suitable to manufacture small housings and unconventional shapes which are typically required for certain applications like brain or nerve implants.

In the wet ionic environments, failure of the electronics in the active implantable devices can occur due to the water molecule and ion ingress through the protective layers. These first cause parameter changes in the passive and active components of the devise. Eventually, they may cause shorts and/or hard opens.

Due to the micro and sub-micrometer scale of the devices the minimal ingress of the water molecules and ions may lead to performance loss or partly or even total failure of the device. For this reason, long-term reliability testing is desirable to study effects of encapsulation performance of the protective coating and/or housing of the device.

Also, if the protective coating or housing degrades, the level of degradation needs to be monitored in order to ensure the correct operation of the device.

The proposed resistance measurement system is not only highly suitable for a wide variety of applications such as multi-modal lab-on-chip applications, DNA

sequencing, bio-compatible polymer encapsulation research, electronic security monitor for tampering, and radiation-hardening/monitoring of chips, but in particular for the above mentioned scenario of measuring the electrical resistance to determine and monitor the degradation housing, the protective layer or other type of encasement of the active implantable device.

Conventional resistance measurement systems for determining degradation and integrity of the active implantable devices rely on potentiostats. These potentiostats are used mainly in electrochemistry, for example to determine how much metals are present in drinking water. Potentiostats apply a certain potential to an electrode and the number of electrons on the electrode is thereby reduced or increased. This causes the liquid to be triggered to deliver or consume electrodes to compensate for this. The current through the electrode can be measured by the potentiostat and the current is compared to the current through a reference electrode, from the degradation and integrity of the device can be derived. Potentiostats are however analog components which consume high amounts of power and have a large dimensional footprint which makes them unsuitable for applications such as in-situ measuring of the electrical resistance of active implantable devices.

The proposed resistance measurement system may be implemented through integrated components such that the power consumption is very low, and the footprint is kept very small. The proposed system comprises one or more sensors, e.g. an array of sensors which may be organized in a two-dimensional array of columns and rows.

Each of the sensors comprises a node, a switching unit and a voltage sensor. The node comprises a stack of successive electrically conductive layers, said stack comprising a layer which comprises a charge holding capacitor arranged for pre charging said capacitor to a predetermined charge level, and a plurality of sensing layers, wherein each of said sensing layers being mutually electrically isolated from each other. The node is comprised of at least one capacitor such that the capacitor and preferably a sensor plate of the stack can be charged with a predetermined charge level or capacity or voltage level. This node is arranged to be operating in charge modus and in a floating modus. In the charge modus, the node is pre-charged to the predetermined charge level and once this level has been reached, the node switches to the floating modus. In the floating modus the node is discharged by the leakage currents at the said node. The switching between the modes is controlled by the switching unit which for example is implemented as a transistor.

The predetermined voltage level may preferably set by the threshold voltage, preferably by an inverter, which may change due to process variation, temperature, supply voltage etc. The electrical resistance may thereby be calculated and based on one or more of the discharge time, capacitance at the node, and approximate threshold set, e.g. by the inverter, which is dynamic. Instead of the threshold value, also the supply voltage may apply.

Once the node is left floating by the switching unit the charge of the capacitor will discharge through the sensing plates or layer, there are comprised of a plurality of sensing plates of which each sensing plate is mutually electrically isolated from each other. Preferably, the sensing plates have a different electrical resistance to the pre-charge node. This may be implemented by use of different isolating materials but preferably by manufacturing the plates in such a way that the plates are located further away from each other. Alternatively, the sensing plates may also have approximately equal electrical resistance. The sensor or sensor element further comprises a voltage sensor to determine the voltage level of the pre-charge node. This way, the voltage level at the pre-charge node may be monitored.

A control unit of the system is not only arranged to control the switching unit to control the switching unit to switch the node between the first state in which the node is charged to a predetermined charge level, and a second state in which the node is floating once the predetermined charge level has been reached, it is also arranged to determining a so called discharge time. In the second state the node discharges through leakage currents, The discharge time is derivable from a clock counter which counts the clock pulses that are generated external or internally in or outside of the system. This discharge time is dependent on the leakage current of the node. Hence, the control unit is able to count the number of clock pulses between switching the node to the open or floating state and the voltage sensor to determine the voltage level of the node to be drop below a predetermined voltage level which may for example be set at Vdd/2.

Accordingly, the RC time constant between the node and the ground may be measured in a very accurate manner and the calculation unit may calculate the electrical resistance of the chip as a proportion between the discharge or RC time and a reference discharge or RC time of a known electrical reference resistance.

The layer of the node with the capacitor and the plurality of sensing plates together form a stack of layers. These layers may be implemented in any standard chip process technology, e.g. in a 0.18pm standard CMOS process. Preferably, there is more than one sensing plate, e.g. more than 2, more preferably, more than 4, even more preferably, and most preferably more than 6. In between the layers of sensing plates, the layers are separated by intermediate electrically isolating layers. The ohmic resistance between two successive sensing plates is very high and may even be in the order of 1015 ohm. Accordingly, high electrical resistance may be measured. The two successive sensing plates are used to monitor the changes in properties of the oxide inside the sensor element.

In an example, wherein said electrically conductive layers comprise silicon dioxide for mutually electrically isolating said layers from each other.

In an example, said electrically conductive layers comprise a metal.

Although, the layers may be electrically isolated by oxidation of the silicon, the electrically conductive layers may be formed from or comprised of metal, but alternatively from use of different metal combinations. This will give the ability to measure the changes in the z direction of the sensor.

In an example, the ratio of surface area coverage between one or more of said sensing layers and said layer comprising said charge holding capacitor is at least approximately 2:1.

In an example, said sensing plates have a higher surface area than said pre-charge node, and wherein said sensing plates preferably have a surface area coverage of above 60%, more preferably, above 70%, more preferably above 80%, even more preferably above 90%, most preferably, of approximately 100%.

The sensing layers or sensing plates, i.e. the bottom layers of the stack, are preferably two or more times bigger, i.e. surface area coverage of the chip, than the layer of the charge holding capacitor, i.e. the top layers of the stack.

The structure surface of the top layer may differ from that of the bottom layers or sensing plates. The sensor plates may for example cover the whole surface area of the sensor element, whereas the top layer of the stack may only cover part of the surface area. In another example, the surface area may have specific shapes such as a H-shape, or shapes with paths which extend to the edges of the surface area of the sensor element.

In an example, said electrically conductive layers are comprised of different metals or metal alloys.

In an example, said system is implemented as an integrated CMOS chip, wherein said pre-charge node and said plurality of sensing plates are implemented as layers of said CMOS chip.

In an example, said control unit is arranged for generating a clock signal.

In an example, said control unit is arranged receiving a clock signal, and wherein control system is further arranged to increase or decrease the clock frequency to a predetermined frequency for increase or decrease of the accuracy of said resistance measurement system.

When a sensor pixel is to be measured, the sensor element is activated, e.g. by receipt of a control signal such as a row and/or column select. After activation, the pre-charge node is charged and the charge at the pre-charge node rises. To maintain the charge, an NMOS MOSCAP may be used as a capacitor component. As soon as the pre-charge node is charged, the charging process may be stopped, and the node is left floating. During this phase the node is discharged by the leakage current at the said node. By control of the output, the signal at the output may also be read out of the element, e.g. if a row read signal is raised. The clock signal is counted by a N-bit counter, e.g. a 20-bit counter, to measure the time between the moment at which the pre-charge node is left floating and the read-out or the moment when the voltage level at the pre-charge node drops below a predetermined level. The counter may also stop when an expiration timer has been exceeded.

By having different clock frequencies, the accuracy of the measurement can be changed. Increase of the frequency will increase accuracy, and the frequency is preferably set at a value between 50Hz and 125kHz. A lower frequency may have lower maximum measurable resistance, but will decrease the time needed to calculate the resistance. Increase of frequency may increase maximum measurable resistance but will also decrease calculation time. With application in with a low expected degradation of the housing of the device, such high frequencies may be very suitable.

In an example, said control unit is arranged to control said switching unit to switch from said second to said first state when said discharge time exceeds a predetermined time-out.

In an example, said sensor comprising a sensor array having a plurality of pixels arranged in rows and columns, each pixel comprising a sensor according to any of the examples indicated above.

In an example, said electrically conductive layers of adjacent pixels in said array are comprised of different metals or metal alloys.

In a second aspect, there is provided, a bio-implantable chip, comprising a resistance measurement system according to any of the aspects and examples indicated above.

In a third aspect, there is provided, a method of manufacturing a sensor for a for a resistance measurement system according to any of the aspects and examples indicated above. The method comprising the steps of:

providing a base sensor array substrate comprising a stack of successive electrically conductive metal layers;

providing base sensor cells comprising sensor capacitance plates into said base sensor array on the top two metal layers of said stack of successive electrically conductive metal layers;

providing standard cells for each of the remaining cells of said base sensor array;

provide routing to each of said cells of said base sensor array for control and readout of each of said cells;

provide a restricting in the routing of each of said cells of said base sensor array other than said top two metal layers of said stack of successive electrically conductive metal layers;

replace said base sensor cells with a copy thereof having bigger sensor capacitance plates.

The invention will hereinafter be further clarified with reference to the drawing of exemplary embodiments of a filter network according to the invention that is not limiting as to the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawing:

figure 1a shows a simplified model of a resistance measurement a resistance measurement system in accordance with an embodiment of the invention;

figure 1b shows a discharge operation in accordance with the model figure 1 ;

figure 2 shows a more detailed circuit representation of resistance measurement system in accordance with an embodiment of the invention;

figure 3 shows a timing schedule of the measurement of the

sensor elements of a resistance measurement system in accordance with an embodiment of the invention;

figure 4 shows the ingress of water and ions through the encapsulating layers of a chip;

figure 5 shows an implemented sensor array in accordance with an embodiment of the invention;

figure 6 shows a structure of the stack of electrically conductive layers in accordance with an embodiment of the invention;

figure 7 shows a manufacturing method or design flow in accordance with an aspect of the invention.

Whenever in the figures the same reference numerals are applied, these numerals refer to the same parts.

DETAILED DESCRIPTION

FIG. 1a shows a schematic representation and simplified model 100 of a resistance measurement system in accordance with an embodiment of the invention. The model 100 is able to measure electrical resistance which can for example be used to monitor the integrity monitoring of bio-implantable chips.

Fig. 1a shows a power source 101 which generates a voltage which can be applied to node n1 105. Whether or not node n1 is provided with the source voltage of the power supply Vdd 101 is defined by the state of the switching unit 106. The switching unit 106 is thus arranged for connecting and disconnecting a charge holding capacitor. The capacitor Cox 103 represents the total capacitance at the node n1 105, which is not only formed by the charge holding capacitor but by the sum of the charge holding capacitor and the sensor capacitor.

The node n1 105 is the node that is charged and subsequently left floating by control of the switch 106, which is preferably a transistor implemented as a MOS transistor. The resistance Rox is the resistance of the oxide of the sensor which represents the irregularities in the oxide structure. The component Rshunt 104 is the resistance which represents the leakage current of the elements connected to the node n1 105.

The model shown in Fig. 1a represents a parallel RC circuit. Once the switch is open, the charge on the capacitor will discharge through the resistors as in accordance with a discharge pattern as shown in Fig. 1b. The voltage at n1 105 and thus also at the output 107 is equal to Vdd 101 just before the switch 106 opens. Just after the switch opens, the voltage at n1 is given by

V„i (t) = VDD e t/Rcq Ccq

Where Req = R0x//Rshunt and Ceq is the combination of all the capacitances to ground at node n1 105. By measuring the time it takes for node n1 105 to be discharged to a specific value, i.e. to the predetermined discharge voltage level, which in the example of fig. 1a and 1b is VDD/2, the RC time constant between n1 105 and ground may be measured to a very high accuracy. For a predetermined discharge voltage level of VDD/2, the discharge time and the RC time constant at n1 are given by

Tdischarge - In (2) Req Ceq

and

RegCeg — In (2) / Tdischarge

In Fig. 2 a more detailed implementation 200 of the design of the resistance measurement system is shown. This embodiment 200 may be implemented in standard CMOS architecture. The implementation uses logic gates from a standard cell library and consists of 3-state buffers, an inverter a D-latch 203 with active low reset, a MOSCAP NM1 201 , a high threshold PMOS transistor MP1 205, and sensing plates 202 to sense the change in oxide over the pixel.

The MOSCAP 201 is used to hold charge and also to reduce the effect of parasitic capacitances and capacitance variation at n1 due to the process mismatch.

The sensor or pixel element 200 is initiated by control of the enable or row select 206. The row select enables the sensor element 200 and when the switching unit or MP1 205 is switched the node n1 is charged to Vdd. Here 205 is used for reducing the total leakage current of the node n1. In Fig. 2 also a 3-state buffer is shown which enables charging the node n1 to VDD. The buffer also allows ending the charging process by turning off both MP1 and the input 3-state buffer, by which node n1 is floating. The output 3-state buffer is preferred for use in for an array implementation.. Once Vdd level has been reached, the switching unit may disconnect node n1 from the Vdd and leave the capacitor 201 and sensor plates 202 floating. The charge in capacitor may discharge through the sensing plates 202 and read out of the sensor via 203.

The control and timing of the sensor element or pixel 200 is shown in Fig. 3. When a sensor pixel 200 is to be measured, the Row enable signal 206 for the chosen pixel row is raised for a clock cycle. During this cycle, the input 3-state buffer and the high-threshold PMOS transistor MP1 205 are turned on, charging node n1 to VDD. To keep the node 201 charged for a longer time, an NMOS MOSCAP is used as charge holding element. Furthermore, by increasing the capacitance at n1 , the effects of pixel-to-pixel variation due to process mismatch is reduced. As soon as node n1 is charged, the output of the latch 203 is automatically set to VDD, as both the D input and enable signals of the latch are connected to VDD. In the next clock cycle two things happen: i) Row enable is lowered, stopping the charging process, turning off both MP1 and the input 3-state buffer, and leaving node n1 floating, and ii) Row read signal is raised to read the pixel output at the column output.

During operation, the control unit or measurement engine sets both the row and the column to be measured. Therefore, as soon as the pixel output is enabled and raised (Q output of the latch is already at VDD), an N-bit counter in the control unit starts counting with CLK. The count stops when either node n1 is discharged below a predetermined discharge voltage level (VDD/2) of the latch and when the latch is reset or a count of 2N - 1 is reached.

The self-reset process of the latch in Figure 2 for realizing oxide change measurement is as follows. When node n1 is left floating, there are no direct discharge paths for the pre-charge node 201 to discharge except the extremely high resistance discharge path through MP1 205 and the output of input 3-state buffer, and through the resistance of the oxide 202, which represents the irregularities in the structure of the oxide, and the ions due to the wet environment. Therefore, the variation in discharge timing of n1 is used to measure the degree of resistance and capacitance changes of the S1O2 layer between two metal layers, which act as the sensing plates. Finally, the time it takes n1 to discharge to VDD/2 is measured to a time count and calculated with the calculation unit the measured resistance using this time count.

If there are no ions in the S1O2 layer between two successive metal layers, the resistance will be very high (in the order of 1015 ohms). However, as the chip integrity is breached and water molecules and ions penetrate first the passivation layer, and later the lower S1O2 layers, there will be multiple changes: i) Conductance will increase (resistance will reduce), and ii) due to a possible oxide damage, capacitance of the S1O2 will increase. In such a case, upon monitoring a lower discharge time count, the control unit may determine that the reduction in the resistance is higher than the increase in the capacitance. Moreover, the discharge time of n1 is reduced in proportion to the reduced resistance (representing the number of ions and molecules in the oxide).

Fig. 5 shows a system implementation of the resistance measurement system 500 for measuring electrical resistance for integrity monitoring of bio implantable chips, said resistance measurement system comprises a sensor array 501 having 23 columns and 234 rows of sensors. The 23 columns may be ready 504 and the rows may be enabled by 505 and read-out through 506. Each sensor of the array 501 comprises a node comprising a charge holding capacitor in the top layer(s) arranged for pre-charging the capacitor to a predetermined charge level, a switching unit arranged for connecting and disconnecting the charge holding capacitor of the node with a power supply, and sensing plates, wherein each of the sensing plates being mutually electrically isolated from each other and from the node, and a voltage sensor arranged for determining a voltage level of the node.

It is expressed that the embodiment explained above demonstrates a sensor array with 23 by 234 sensor elements or pixels. This is merely by way of example, the skilled person will appreciate that the invention may be embodied in a sensor array with any other M-rows by N-columns sensor array layout.

The system 500 further comprises a measurement engine 502 which may consist of a control unit to control operation of the sensor and a calculation unit for final calculating of the electrical resistance of the chip. The measurement engine 502 or control unit has 4 in/outputs, e.g. a data in, a data out, a clock in and a reset.

The successive metal layers which are used as the sensing plates to monitor the changes in the properties of the oxide over the pixel are shown in Fig. 6. The top plate 601 of the sensing structure is connected to node n1 and the bottom plate 602 is connected to ground. In the presented embodiment, there are three different versions of the sensor pixel shown in Fig. 2, with different metal layer pairs, namely M6-M5, M5-M4, and M4-M3. Taking into account the probability of failure over a cell area being uniform, it can be calculated that, to be able to capture the change in the oxide with maximum probability, the upper plate area should is preferably half of the area of the bottom plate, and to realize such a structure with regularity, the design of Fig. 6 is presented. In the layout of the sensor array, cells with different sensor capacitors are placed alternatingly, e.g., an M6-M5 cell is followed by an M5-M4 cell, which is followed by an M4-M3 cell, both in the x and y directions. In the extracted layout, it was determined that capacitance at n1 varies between 23.5 and 24.5fF (17.5fF from the MOSCAP), depending on the used metal layers. Furthermore, using different metal combinations gives the ability to measure the changes in the z direction as well.

From Fig. 6 it can be observed that the surface area coverage of the layers differs from one another. The ratio between the top and bottom layers is preferably 2, meaning that the lower layers have a surface area coverage which is 2 times bigger than that of the higher layer. In case of a surface area coverage with is less than 100% other shapes than the shape demonstrated in Fig. 6 may be used as well. The skilled person will appreciate which shapes may be applicable.

The transistors as described in the embodiments are of the MOS type, unless specified otherwise. The transistors are specified in two polarities, NMOS and PMOS, having their specific characteristics. Unless specifically specified, the circuits may be embodied using other polarity types than described in conjunction with the embodiments. Transistors performing a functionality of switching may be replaced by other switching devices as well. That could be other types of transistors or yet another type of switches

The various embodiments of the first aspect discussed above are preferably embedded in an integrated semiconductor circuit. Referring to the figures, the pre-charge node may be provided as a MOSCAP.

Expressions such as “comprise”, “include”, “incorporate”, “contain”, “is” and “have” are to be construed in a non-exclusive manner when interpreting the description and its associated claims, namely construed to allow for other items or components which are not explicitly defined also to be present. Reference to the singular is also to be construed in be a reference to the plural and vice versa.

In the description above, it will be understood that when an element such as layer, region or substrate or components of a system are referred to as being “on”, “onto” or “connected to” another element, the element is either directly on or connected to the other element, or intervening elements may also be present.

Furthermore, the invention may also be embodied with less components than provided in the embodiments described here, wherein one component carries out multiple functions. Just as well may the invention be embodied using more elements than depicted in the Figures, wherein functions carried out by one component in the embodiment provided are distributed over multiple components.

A person skilled in the art will readily appreciate that various parameters disclosed in the description may be modified and that various embodiments disclosed and/or claimed may be combined without departing from the scope of the invention.

It is stipulated that reference signs in the claims do not limit the scope of the claims, but are merely inserted to enhance the legibility of the claims.