1. WO2026174513 - MEMORY SYSTEM WITH INTERLEAVED ROW REFRESH TO ADDRESS ROW HAMMER DEGRADATION

Publication Number WO/2026/174513

Publication Date 27.08.2026

International Application No. PCT/CN2025/078403

International Filing Date 21.02.2025

IPC

G11C 11/406 2006.1

G	PHYSICS
11	INFORMATION STORAGE
C	STATIC STORES
11	Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21	using electric elements
34	using semiconductor devices
40	using transistors
401	forming cells needing refreshing or charge regeneration, i.e. dynamic cells
406	Management or control of the refreshing or charge-regeneration cycles

G11C 11/406 2006.1

G	PHYSICS
11	INFORMATION STORAGE
C	STATIC STORES
11	Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21	using electric elements
34	using semiconductor devices
40	using transistors
401	forming cells needing refreshing or charge regeneration, i.e. dynamic cells
406	Management or control of the refreshing or charge-regeneration cycles

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Applicants

• QUALCOMM INCORPORATED [US]/[US]
• LIN, Benfeng [CN]/[CN](WS)
• MA, Xiaodong [CN]/[CN](WS)
• TRAN, Sang [US]/[US](WS)
• LI, Hao [CN]/[CN](WS)
• GUO, Can [CN]/[CN](WS)
• YANG, Chunmin [CN]/[CN](WS)
• VUONG, Hung [US]/[US](WS)
• ZHANG, Rongtian [US]/[US](WS)

Inventors

• LIN, Benfeng
• MA, Xiaodong
• TRAN, Sang
• LI, Hao
• GUO, Can
• YANG, Chunmin
• VUONG, Hung
• ZHANG, Rongtian

Agents

• NTD PATENT & TRADEMARK AGENCY LTD.

Priority Data

Publication Language English (en)

Filing Language English (en)

Designated States

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AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CV, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IQ, IR, IS, IT, JM, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, MG, MK, MN, MU, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UY, UZ, VC, VN, WS, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, CV, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SC, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, ME, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)

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Title

(EN) MEMORY SYSTEM WITH INTERLEAVED ROW REFRESH TO ADDRESS ROW HAMMER DEGRADATION

(FR) SYSTÈME DE MÉMOIRE À RAFRAÎCHISSEMENT DE RANGÉE ENTRELACÉ POUR RÉSOUDRE LA DÉGRADATION DUE AUX ATTAQUES RÉPÉTÉES

Abstract

(EN) Aspects disclosed include a memory system with interleaved row refresh to address row hammer degradation. The memory system includes a refresh control circuit and a memory block. The memory block includes a first plurality of memory cell rows and a second plurality of memory cell rows, wherein the first plurality of memory cell rows is spatially interleaved with the second plurality of memory cell rows. In response to receiving a first number of commands to open the first plurality of memory cell rows which exceed a first threshold, the refresh control circuit is configured to refresh the second plurality of memory cell rows. The memory system advantageously addresses the known problem of row hammering while not expending energy refreshing the first plurality of memory cell rows, in contrast to conventional approaches which refresh all the rows.

(FR) Des aspects divulgués concernent un système de mémoire à rafraîchissement de rangée entrelacé pour résoudre la dégradation due aux attaques répétées. Le système de mémoire comprend un circuit de commande de rafraîchissement et un bloc de mémoire. Le bloc de mémoire comprend une première pluralité de rangées de cellules de mémoire et une seconde pluralité de rangées de cellules de mémoire, la première pluralité de rangées de cellules de mémoire étant entrelacée spatialement avec la seconde pluralité de rangées de cellules de mémoire. En réponse à la réception d'un premier nombre de commandes pour ouvrir la première pluralité de rangées de cellules de mémoire qui dépassent un premier seuil, le circuit de commande de rafraîchissement est configuré pour rafraîchir la seconde pluralité de rangées de cellules de mémoire. Le système de mémoire résout de manière avantageuse le problème connu d'attaques répétées sans dépenser d'énergie pour rafraîchir la première pluralité de rangées de cellules de mémoire, contrairement aux approches classiques qui rafraîchissent toutes les rangées.

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