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1. (WO2004010666) FSK RECEIVER HAVING A VARIABLE THRESHOLD SLICER STAGE AND CORRESPONDING METHOD

Pub. No.:    WO/2004/010666    International Application No.:    PCT/IB2003/003028
Publication Date: Jan 29, 2004 International Filing Date: Jul 8, 2003
IPC: H04L 25/06
Applicants: KONINKLIJKE PHILIPS ELECTRONICS N.V.
PAYNE, Adrian, W.
CALDWELL, Richard, J.
Inventors: PAYNE, Adrian, W.
CALDWELL, Richard, J.
Title: FSK RECEIVER HAVING A VARIABLE THRESHOLD SLICER STAGE AND CORRESPONDING METHOD
Abstract:
A receiver having a variable threshold slicer stage, comprises a demodulator (14) for providing asynchronously samples of over-sampled raw demodulated data, a shift register (60) for delaying the over-sampled data by up to 2 bit periods. Samples in stages (62, 72) corresponding to substantially the mid-points in two successive bit periods are combined to form a signal (ƒXn) to be applied to a bit slicer (22). A bit stream signal from the bit slicer (22) is delayed by two concatenated shift registers (30,32) for 2 bit periods and is contemporaneously applied to a clock recovery circuit (74) for producing clock signals at the data rate for sampling the delayed sliced signal (Bn-2) at the center of bit to produce an output signal (34).