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1. WO2018125140 - METAL OXIDE THIN FILM TRANSISTORS WITH CONTROLLED HYDROGEN

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[ EN ]

Claims

What is claimed is:

1. A semiconductor device, comprising:

a substrate;

a gate electrode above the substrate;

a gate dielectric layer conformally covering the gate electrode and the substrate; a hydrogen diffusion barrier (HDB) layer above the gate dielectric layer;

a channel layer above the HDB layer, wherein the channel layer includes a source area and a drain area; and

a source electrode coupled to the source area, and a drain electrode coupled to the drain area.

2. The semiconductor device of claim 1, further comprising:

another HDB layer above the channel layer, wherein the source electrode is through the another HDB layer and coupled to the source area, and the drain electrode is through the another HDB layer and coupled to the drain area.

3. The semiconductor device of claim 1, further comprising:

an interlayer dielectric (ILD) layer above the channel layer, wherein the source electrode is through the ILD layer and coupled to the source area, and the drain electrode is through the ILD layer and coupled to the drain area.

4. The semiconductor device of any of claims 1-3, wherein the HDB layer includes TiO2, Al2O3, AlN, doped-TiO2, or doped-Al2O3.

5. The semiconductor device of any of claims 1-3, wherein the channel layer includes zinc (Zn) and oxygen (O).

6. The semiconductor device of any of claims 1-3, wherein the channel layer includes InGaZnO (IGZO), amorphous InGaZnO (a-IGZO), crystal-like InGaZnO (c-IGZO), GaZnON, ZnON, or C-Axis Aligned Crystal (CAAC).

7. The semiconductor device of any of claims 1-3, wherein the channel layer has a thickness in a range of about 10 nm to about 100 nm.

8. The semiconductor device of any of claims 1-3, wherein the gate dielectric layer includes silicon oxide (SiO2), silicon nitride (SiNx), yttrium oxide (Y2O3), silicon oxynitride (SiONy), aluminum oxide (Al2O3), hafnium(IV) oxide (HfO2), tantalum oxide (Ta2O5), or titanium dioxide (TiO2).

9. The semiconductor device of any of claims 1-3, wherein the source electrode or the drain electrode includes titanium (Ti), molybdenum (Mo), gold (Au), platinum (Pt), aluminum (Al), nickel (Ni), copper (Cu), chromium (Cr), or an alloy of Ti, Mo, Au, Pt, Al Ni, Cu, Cr.

10. The semiconductor device of any of claims 1-3, wherein the substrate includes a glass substrate, a metal substrate, or a plastic substrate.

11. A computing device comprising:

a processor;

a memory device coupled to the processor; and

a display coupled to the processor, the display including a transistor, and the transistor including:

a substrate;

a gate electrode above the substrate;

a gate dielectric layer conformally covering the gate electrode and the substrate;

a hydrogen diffusion barrier (HDB) layer above the gate dielectric layer; a channel layer above the HDB layer, wherein the channel layer includes a source area and a drain area; and

a source electrode coupled to the source area, and a drain electrode coupled to the drain area.

12. The computing device of claim 11, wherein the transistor further includes:

another HDB layer above the channel layer, wherein the source electrode is through the another HDB layer and coupled to the source area, and the drain electrode is through the another HDB layer and coupled to the drain area.

13. The computing device of claim 11, wherein the transistor further includes: an interlayer dielectric (ILD) layer above the channel layer, wherein the source electrode is through the ILD layer and coupled to the source area, and the drain electrode is through the ILD layer and coupled to the drain area.

14. The computing device of any of claims 11-13, wherein the HDB layer includes TiO2, Al2O3, AlN, doped-TiO2, or doped-Al2O3.

15. The computing device of any of claims 11-13, wherein the channel layer includes InGaZnO (IGZO), amorphous InGaZnO (a-IGZO), crystal-like InGaZnO (c-IGZO), GaZnON, ZnON, or C-Axis Aligned Crystal (CAAC).

16. The computing device of any of claims 11-13, wherein the computing device is a wearable device or a mobile computing device, the wearable device or the mobile computing device including one or more of an antenna, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera coupled with the processor.

17. A method for forming a semiconductor device, the method comprising:

forming a gate electrode above a substrate;

forming a gate dielectric layer conformally covering the gate electrode and the substrate;

forming a hydrogen diffusion barrier (HDB) layer above the gate dielectric layer; forming a channel layer above the HDB layer;

forming a source area and a drain area within the channel layer; and

forming a source electrode coupled to the source area, and a drain electrode coupled to the drain area.

18. The method of claim 17, further comprising:

forming another HDB layer above the channel layer, wherein the source electrode is formed through the another HDB layer and coupled to the source area, and the drain electrode is formed through the another HDB layer and coupled to the drain area.

19. The method of claim 17, further comprising:

forming an interlayer dielectric (ILD) layer above the channel layer, wherein the source electrode is formed through the ILD layer and coupled to the source area, and the drain electrode is through the ILD layer and coupled to the drain area.

20. The method of claim 17, further comprising:

forming a buffer layer above the substrate, and wherein the forming the gate electrode above the substrate includes forming the gate electrode above the buffer layer.

21. The method of any of claims 17-20, wherein the gate dielectric layer includes SiO2 or SiNx, and wherein the forming the gate dielectric layer includes forming the gate dielectric layer by plasma enhanced chemical vapor deposition (PECVD) at 1000C to 2000C.

22. The method of any of claims 17-20, wherein the HDB layer includes TiO2, Al2O3, AlN, doped-TiO2, or doped-Al2O3, and wherein the forming the HDB layer includes forming the HDB layer by physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD).

23. The method of any of claims 17-20, wherein the forming the channel layer includes depositing an amorphous InGaZnO (a-IGZO) film at 250C to 3000C by radio frequency (RF) sputtering, direct current (DC) sputtering, magnetron sputtering, ALD, plasma enhanced atomic layer deposition (PEALD), or PECVD.

24. The method of any of claims 17-20, wherein the forming the channel layer includes simultaneously sputtering InGaZnO (IGZO) and ZnO at a temperature in a range of 250C to 4000C by radio frequency (RF) sputtering, direct current (DC) sputtering, or magnetron sputtering, to form a crystal-like InGaZnO (c-IGZO) film.

25. The method of any of claims 17-20, wherein the channel layer includes InGaZnO (IGZO), amorphous InGaZnO (a-IGZO), crystal-like InGaZnO (c-IGZO), GaZnON, ZnON, or C-Axis Aligned Crystal (CAAC).