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Machine translation
18. (WO2011066459) MULTIPLE-MEMORY APPLICATION-SPECIFIC DIGITAL SIGNAL PROCESSOR
Note: Text based on automatic Optical Character Recognition processes. Please use the PDF version for legal matters

CLAIMS

What is claimed is:

1. An integrated circuit device, comprising:

a circuit board; and

one or more digital signal processors implemented thereon, each comprising: a data unit comprising:

a function core configured to perform a specific mathematical expression in order to perform at least a portion of a specific application; and

an instruction memory storing one or more instructions configured to send commands to a control unit and the data unit to perform the specific application; and

the control unit configured to control a flow of data between a plurality of memory banks and the function core for performing the specific application; the plurality of memory banks coupled to the each of the one or more digital signal processors and comprising at least two or more local memory banks integrated onto the circuit board.

2. The integrated circuit device of claim 1, wherein the plurality of memory banks further comprise one or more external memory banks coupled to at least one of the one or more digital signal processors.

3. The integrated circuit device of claim 1, wherein the data unit further comprises at least one of a one or more registers such as an instruction register, and memory address register, and one or more counters such as a program counter.

4. The integrated circuit device of claim 1, wherein the instruction memory comprises at least two instructions.

5. The integrated circuit device of claim 4, wherein the at least two instructions comprise a first instruction for the specific application and a second instruction for halting the digital signal processor.

6. The integrated circuit device of claim 5, wherein the instruction memory further comprises instructions for loading input data for performing the specific mathematical expression, and storing output data of the function core.

7. The integrated circuit device of claim 1, wherein the instruction memory is a part of the data unit and is separate from the plurality of memory banks coupled to the data unit.

8. The integrated circuit device of claim 1, wherein the function core performs one or both of fixed point operations and floating point operations.

9. The integrated circuit device of claim 1, wherein the function core comprises one or more inputs for receiving input data for performing the specific mathematical expression, and further comprises one or more outputs comprising a result of the specific mathematical expression performed.

10. The integrated circuit device of claim 1, wherein the function core comprises a plurality of function cores, each performing a portion of the specific mathematical expression.

11. The integrated circuit device of claim 1 , wherein the function core is configured such that an output is provided for the specific mathematical expression at every clock cycle.

12. The integrated circuit device of claim 1, comprising at least two digital signal processors, wherein the at least two digital signal processors comprise at least one shared memory bank, such that the at least two digital signal processors share the at least one shared memory bank.

13. The integrated circuit device of claim 12, wherein the at least one shared memory bank comprises a local memory bank integrated onto the circuit board.

14. The integrated circuit device of claim 12, wherein the at least one shared memory bank comprises an external memory bank coupled to the circuit board.

15. A method, comprising:

generating one or more digital signal processors, wherein generating each of the one or more digital signal processors comprises:

generating a data unit comprising:

generating a function core configured to perform a specific mathematical expression in order to perform at least a portion of a specific application; and

generating an instruction memory storing one or more instructions configured to send commands to a control unit and the data unit to perform the specific application;

generating the control unit configured to control a flow of data between a plurality of memory banks and the function core for performing the specific application;

loading the one or more digital signal processors onto a circuit board; and coupling each of the one or more digital signal processors to the plurality of memory banks comprising coupling each of the one or more digital signal processors to at least two or more local memory banks integrated onto the circuit board.

16. The method of claim 15, wherein coupling the data unit to the plurality of memory banks further comprises coupling each of the one or more digital signal processors to at least one or more external memory banks.

17. The method of claim 15, wherein the instruction memory is a part of the data unit and is separate from the plurality of memory banks coupled to the data unit.

18. The method of claim 15, wherein the function core comprises one or more function cores, each performing a portion of the specific mathematical expression.

19. The method of claim 15, wherein each of the one or more digital signal processors comprises a bit stream configured to be loaded onto the circuit board.

20. A tangible computer-readable storage medium having computer readable instructions that are configured to perform a method when executed by a processor, the method comprising:

generating one or more digital signal processors, wherein generating each of the one or more digital signal processors comprises:

generating a data unit comprising:

generating a function core configured to perform a specific mathematical expression in order to perform at least a portion of a specific application; and

generating an instruction memory storing one or more instructions configured to send commands to a control unit and the data unit to perform the specific application;

generating the control unit configured to control a flow of data between a plurality of memory banks and the function core for performing the specific application;

loading the one or more digital signal processors onto a circuit board; and coupling the each of the one or more digital signal processors to the plurality of memory banks comprising coupling the data unit of each of the one or more digital signal processors to at least two or more local memory banks integrated onto the circuit board.