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Machine translation
1. (WO2001091129) DYNAMIC CONFIGURATION OF STORAGE ARRAYS
Note: Text based on automatic Optical Character Recognition processes. Please use the PDF version for legal matters

WHAT IS CLAIMED IS:
1. A reconfigurable memoryflO, 50, 100] comprising:

M bit lines[12], where M>1;

a plurality of row lines[13];

an array[l 1] of memory storage cells[15], each memory storage cell[15] storing a data value and comprising circuitry for coupling that data value to one of said bit lines[12] in response to a row control signal on one of said row lines[l 3];

a row select circuit[14] for generating said row control signal on one of said row lines[13] in response to a row address being coupled to said row select circuit[14], said row select circuit[14] comprising a memory for storing a mapping of said row addresses to said row lines[13], said mapping determining which of said row lines[13] is selected for each possible value of said row address; and

a contra ller[40] for determining that one of said memory cells is defective and for altering said mapping to eliminate references to that row line[13] that causes that defective storage cell to couple a data value to one of said bit lines [12].

2. The reconfigurable memory[10, 50, 100] of Claim 1 wherein said controller[40] tests all of said memory storage cells[15] to determine if any of said memory storage cells[15] is defective each time power is applied to said controller[40] and wherein said controller[40] eliminates references in said mapping to row lines[13] that cause said detected defective storage cells to couple data values to said bit lines [12].

3. The reconfigurable memory[10, 50, 100] of Claim 2 wherein said controller[40] assigns a row address to each of said reference lines that was not eliminated because of a defective memory cell and wherein said controller[40] communicates the maximum number of rows available for storing data values after the elimination of said defective row references.

4. The reconfigurable memory[10, 50, 100] of Claim 1 wherein said memory further comprises a single cell memory[60] for storing a plurality of single data values, each data value corresponding to one of said row addresses and one of said bit lines [12] and wherein said controller[40] further comprises a circuit for causing that data value stored in said single cell memory [60] for one of said row addresses and bit lines [12] to replace that value stored in said memory storage cell[15] coupled to that bit line[12] when that row address is coupled to said row select circuit[14].

5. The reconfigurable memory[10, 50, 100] of Claim 1 further comprising a word assembly circuit[23] for selecting N bit lines[12] from said M bit lines[12], where N is less than or equal to M, said word assembly circuit[23] comprising a memory for storing a mapping specifying said N bit lines[12] for each possible row address, wherein said controller[40] alters said mapping to eliminate a reference in said mapping to a bit line[12] that causes a defective storage cell to couple data to a bit line[13] in response to one of said row addresses.

6. The reconfigurable memory[10, 50, 100] of Claim 5 wherein said word assembly circuit[23] comprises a cross-connect switch for coupling said M bit lines[12] to N data lines.

7. The reconfigurable memory[10, 50, 100] of Claim 6 wherein said cross-connect switch[23] is partially populated such that only selected ones of said M bit lines[12] can be connected to any particular data line.

8. The reconfigurable memory[10, 50, 100] of Claim 1 further comprising an error correcting circuitβ 1] for detecting errors in data words, said error correcting circuit[31] generating a corrected data word and an error data word from N data values coupled thereto, said error data word indicating which of said N data values, if any, was erroneous; and

a word assembly circuit for connecting N of said M bit lines [12] to said error correcting circuit[31], where N is less than or equal to M; wherein said control circuit is connected to said error correcting circuital] and receives said error data words and said row addresses, said control circuit altering said mapping in said row select circuit[14] in response to said error data words.

9. The memory of Claim 8 wherein N<M and wherein said word assembly circuit comprises a cross-connect circuit for connecting N of said M bit lines[12] to said error correcting circuit[31].

10. The memory of Claim 8 further comprising an error correcting code generating circuit[30] for generating an error correcting data word from a data word, said error correcting data word being stored in a location corresponding to said data word in said memory.

11. The memory of Claim 10, wherein said error correcting data word is stored in the same row of memory cells as said data word used to generate said error correcting data word.