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1. WO2007097791 - POWER CONSERVATION VIA DRAM ACCESS

Note: Text based on automatic Optical Character Recognition processes. Please use the PDF version for legal matters

[ EN ]

CLAIMS
What is claimed is:
1. A method comprising:
storing at least a portion of non-cacheable data in a cache associated with a microprocessor configured to operate in a buffer mode.

2. The method of claim 1 , wherein the non-cacheable data is display refresh data (DRD).

3. The method of claim 1 wherein the buffer mode comprises allowing the microprocessor to operate in a low power state.

4. The method of claim 1 wherein the storing comprises utilizing lower limit and upper limit registers to specify the at least a portion of the non-cacheable data to match the cache size.

5. The method of claim 1 wherein the storing comprises utilizing a base register and an offset limit register to specify the at least a portion of the non-cacheable data such that its size matches to the cache size.

6. The method of claim 1 wherein the storing comprises utilizing at least one request property for identifying a source of the non-cacheable data.

7. The method of claim 1 wherein a direct mapped policy is utilized in the buffer mode.

8. The method of claim 1 wherein the storing is initiated by a normal mode to buffer mode event.

9. The method of claim 1 wherein the normal mode to buffer mode event comprises the microprocessor being in a reduced power state.

10. The method of claim 1 wherein the non-cacheable data is stored in the cache such that the amount of non-cacheable data never exceeds the cache size.

11. A microprocessor system comprising: a processor; and
a cache system, the cache system comprising a cache and a controller coupled to the cache, the controller configured to store at least a portion of non-cacheable data in the cache, when the microprocessor operates in the buffer mode.

12. The microprocessor of claim 11 , wherein the non-cacheable data is display refresh data (DRD).

13. The microprocessor of claim 11 wherein the buffer mode comprises allowing the microprocessor system to operate in a low power state.

14. The microprocessor of claim 11 wherein the controller is further configured to use a lower limit register and an upper limit register to specify the at least a portion of the non-cacheable data.

15. The microprocessor of claim 11 wherein the controller is further configured to use a base register and an offset limit register to specify the at least a portion of the non-cacheable data to match the cache size.

16. The microprocessor of claim 11 wherein storing comprises utilizing at least one request property for identifying a source of the non-cacheable data.

17. The microprocessor of claim 11 wherein the controller is further configured to use a direct mapped policy when the microprocessor is in the buffer more.

18. The microprocessor of claim 11 wherein a normal mode to buffer mode event initiates storing by the controller, at least a portion of non-cacheable data in the cache.

19. The microprocessor of claim 11 wherein the normal mode to buffer mode event comprises the microprocessor being in a reduced power state.

20. The microprocessor of claim 11 wherein the controller is further configured to store non-cacheable data in the cache such that the amount of non-cacheable data never exceeds the cache size.

21. A computer readable medium containing program instructions for:
storing at least a portion of non-cacheable data in a cache associated with a microprocessor configured to operate in a buffer mode.

22. A medium readable by a computer system that contains descriptions that generate, when interpreted by the computer system, a circuit comprising:
storing at least a portion of non-cacheable data in a cache associated with a microprocessor configured to operate in a buffer mode.