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1. WO2020142208 - SYSTEM AND METHOD OF FABRICATING DISPLAY STRUCTURES

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[ EN ]

What is claimed is:

1. A method of fabricating display structures; the method comprising:

receiving a wafer which comprises a growth substrate and an epitaxial semiconductor layer grown on a first face of the growth substrate;

patterning the epitaxial semiconductor layer of the wafer from a front face of the epitaxial semiconductor layer to form a common contact;

bonding the common contact to a carrier substrate;

releasing the growth substrate from the epitaxial semiconductor layer to expose a back face of the epitaxial semiconductor layer, the back face opposed from the front face across a thickness of the epitaxial semiconductor layer;

providing individually addressable contacts on the back face of the epitaxial semiconductor layer, such that the common contact, the epitaxial semiconductor layer, and the individually addressable contacts form a set of micro-light emitting diodes (micro- LEDs); and

electrically coupling a set of drive circuitry to the individually addressable contacts to control the micro-LEDs.

2. The method of claim 1 ; further comprising:

patterning the epitaxial semiconductor layer to form a respective discrete semiconductor element for each of the micro-LEDs.

3. The method of claim 1 wherein bonding the common contact to a carrier substrate includes bonding the common contact to a transparent or translucent carrier substrate, where light emission from the micro-LEDs will pass through the transparent or translucent carrier substrate.

4. The method of claim 1 ; further comprising:

growing the epitaxial semiconductor layer on the first face of the growth substrate.

5. The method of claim 1 wherein electrically coupling a set of drive circuitry to the individually addressable contacts to control the micro-LEDs includes electrically coupling a set of complementary metal oxide semiconductor (CMOS) circuits to the individually addressable contacts to control the micro-LEDs.

6. The method of claim 1 ; further comprising:

depositing an insulating layer over individually addressable contacts; and

forming vias in the insulating layer to provide a set of electrical connections to the individually addressable contacts through the insulating layer.

7. The method of claim 6 wherein electrically coupling a set of drive circuitry to the individually addressable contacts to control the micro-LEDs includes electrically coupling a set of thin film transistor (TFT) circuits to the individually addressable contacts to control the micro- LEDs.

8. The method of claim 1 wherein bonding the common contact to a carrier substrate includes bonding the common contact to a translucent carrier substrate that is wavelength selective.

9. The method of claim 1 wherein releasing the growth substrate includes performing a laser lift-off.

10. The method of claim 1 wherein releasing the growth substrate includes polishing the growth substrate.

11. The method of claim 10; further comprising:

removing residue from the polishing of the growth substrate.

12. The method of claim 1 ; further comprising:

adding one or more optical features to the carrier substrate.

13. A method of fabricating display structures; the method comprising:

receiving a wafer which comprises a growth substrate and an epitaxial semiconductor layer grown on a first face of the growth substrate;

patterning the epitaxial semiconductor layer of the wafer from a front face of the epitaxial semiconductor layer to form first conductive contacts at a relatively fine pitch;

depositing an insulating layer over the first conductive contacts;

forming vias in the insulating layer to provide a set of electrical connections to the first conductive contacts through the insulating layer;

depositing second conductive contacts at a relatively coarse pitch that is relatively more coarse than the fine pitch over the insulating layer;

selectively electrically connecting ones of the first conductive contacts, through the vias, to ones of the second conductive contacts using the set of electrical connections, such that the first conductive contacts, the epitaxial semiconductor layer, and the second conductive contacts form a set of micro-light emitting diodes (micro-LEDs);

electrically coupling the second conductive contacts to a set of drive circuitry to control the micro-LEDs; and

bonding the set of drive circuitry to a carrier substrate.

14. The method of claim 13; further comprising:

growing the epitaxial semiconductor layer on the first face of the growth substrate.

15. The method of claim 13; further comprising:

adding one or more optical features to the carrier substrate.

16. The method of claim 13; further comprising:

releasing the growth substrate from the epitaxial semiconductor layer to expose a back face of the epitaxial semiconductor layer, the back face opposed from the front face across a thickness of the epitaxial semiconductor layer.

17. The method of claim 13 wherein electrically coupling the second conductive contacts to a set of drive circuitry to control the micro-LEDs includes electrically coupling a set of thin film transistor (TFT) circuits or a set of complementary metal oxide semiconductor (CMOS) circuits to the second conductive contacts to control the micro-LEDs.

18. The method of claim 13 wherein bonding the set of drive circuitry to a carrier substrate comprises utilizing a material allowing emission of light through the carrier substrate.

19. The method of claim 18 wherein allowing emission of light through the carrier substrate comprises transmitting light at a selected wavelength generated by the micro-LEDs through the carrier substrate.

20. The method of claim 16 wherein releasing the growth substrate includes performing a laser lift-off.

21. The method of claim 16 wherein releasing the growth substrate includes polishing the growth substrate.

22. The method of claim 16 wherein releasing the growth substrate includes etching the growth substrate.

23. The method of claim 13 wherein receiving a wafer which comprises a growth substrate and an epitaxial semiconductor layer grown on a first face of the growth substrate includes receiving a wafer in which the growth substrate is sapphire.

24. The method of claim 13 wherein receiving a wafer which comprises a growth substrate and an epitaxial semiconductor layer grown on a first face of the growth substrate includes receiving a wafer in which the growth substrate is selected from the group consisting of GaN, InP, InGaAs, Si, SiC, and Ge.

25. The method of claim 13 wherein receiving a wafer which comprises a growth substrate and an epitaxial semiconductor layer grown on a first face of the growth substrate includes receiving a wafer in which the epitaxial semiconductor layer is Gallium Nitride.

26. The method of claim 13 wherein receiving a wafer which comprises a growth substrate and an epitaxial semiconductor layer grown on a first face of the growth substrate includes receiving a wafer in which the epitaxial semiconductor layer comprises Silicon.

27. The method of claim 13 wherein receiving a wafer which comprises a growth substrate and an epitaxial semiconductor layer grown on a first face of the growth substrate includes receiving a wafer in which the epitaxial semiconductor layer comprises a material selected from the group consisting of GaN, InP, InGaAs, Si, SiC, and Ge.

28. A method of fabricating display structures; the method comprising:

receiving a wafer which comprises a growth substrate and an epitaxial semiconductor layer grown on a first face of the growth substrate;

patterning the epitaxial semiconductor layer of the wafer from a front face of the epitaxial semiconductor layer to form first conductive contacts at a relatively fine pitch that is finer than a relatively coarse pitch;

depositing an interposer layer on the front face of the epitaxial semiconductor layer over the first conductive contacts;

providing drive circuitry which is electrically coupled to the interposer layer, opposed from the epitaxial semiconductor layer, with a set of second conductive contacts, the second conductive contacts disposed at the relatively coarse pitch that is coarser than the fine pitch; and

selectively electrically connecting ones of the first conductive contacts, through the interposer layer, to ones of the second conductive contacts, such that the first conductive contacts, the epitaxial semiconductor layer, and the second conductive contacts form a set of micro-light emitting diodes (micro-LEDs) controlled by the drive circuitry.

29. The method of claim 28; further comprising:

growing the epitaxial semiconductor layer on the first face of the growth substrate.

30. The method of claim 28 wherein providing drive circuitry comprises electrically coupling a set of thin film transistor (TFT) circuits or a set of complementary metal oxide semiconductor (CMOS) circuits to the interposer layer using the second conductive contacts.

31. The method of claim 28 wherein receiving a wafer which comprises a growth substrate and an epitaxial semiconductor layer grown on a first face of the growth substrate includes receiving a wafer in which the growth substrate is sapphire.

32. The method of claim 28 wherein receiving a wafer which comprises a growth substrate and an epitaxial semiconductor layer grown on a first face of the growth substrate includes receiving a wafer in which the epitaxial semiconductor layer is Gallium Nitride.

33. The method of claim 28 wherein receiving a wafer which comprises a growth substrate and an epitaxial semiconductor layer grown on a first face of the growth substrate includes receiving a wafer in which the epitaxial semiconductor layer comprises Silicon.

34. A method of fabricating display structures; the method comprising:

receiving a wafer which comprises a growth substrate and an epitaxial semiconductor layer grown on a first face of the growth substrate;

patterning the epitaxial semiconductor layer of the wafer from a front face of the epitaxial semiconductor layer to form an interconnect layer comprising drive circuitry;

bonding the interconnect layer to a carrier substrate;

releasing the growth substrate from the epitaxial semiconductor layer to expose a back face of the epitaxial semiconductor layer, the back face opposed from the front face across a thickness of the epitaxial semiconductor layer; and

depositing a color conversion layer on the back face of the epitaxial semiconductor layer, such that the interconnect layer, the epitaxial semiconductor layer, and the color

conversion layer form a set of micro-light emitting diodes (micro-LEDs) controlled by the drive circuitry.

35. The method of claim 34; further comprising:

growing the epitaxial semiconductor layer on the first face of the growth substrate.

36. The method of claim 34; further comprising:

adding a color filter layer to the back face of the epitaxial semiconductor layer, the color filter layer disposed over the color conversion layer.

37. The method of claim 36 wherein releasing the growth substrate includes performing a laser lift-off.

38. The method of claim 36 wherein releasing the growth substrate includes polishing the growth substrate.

39. The method of claim 36 wherein releasing the growth substrate includes etching the growth substrate.

40. The method of claim 39 wherein releasing the growth substrate includes etching the growth substrate following release process operations.

41. The method of claim 34 wherein depositing a color conversion layer comprises depositing a layer of material that includes a phosphor.

42. The method of claim 34 wherein depositing a color conversion layer comprises depositing a layer of material that includes a nanophosphor.

43. The method of claim 34 wherein depositing a color conversion layer comprises depositing a layer of material that includes a quantum dot.

44. The method of claim 34 wherein depositing a color conversion layer comprises adding an epitaxial semiconductor layer.

45. The method of claim 36 wherein adding a color filter layer comprises adding a dielectric filter.

46. The method of claim 36 wherein adding a color filter layer comprises adding a dielectric or metallic mirror.

47. The method of claim 36 wherein adding a color filter layer comprises adding a plasmonic optical element.

48. The method of claim 36 wherein adding a color conversion layer comprises adding a photoluminescent semiconductor structure in which a light emitting bandgap is formed at a desired energy.

49. The method of claim 36 wherein adding a color conversion layer comprises adding a wide bandgap semiconductor doped with activators.

50. The method of claim 34 wherein receiving a wafer which comprises a growth substrate and an epitaxial semiconductor layer grown on a first face of the growth substrate includes receiving a wafer in which the growth substrate is sapphire.

51. The method of claim 34 wherein receiving a wafer which comprises a growth substrate and an epitaxial semiconductor layer grown on a first face of the growth substrate includes receiving a wafer in which the growth substrate is selected from the group consisting of GaN, InP, InGaAs, Si, SiC, and Ge.

52. The method of claim 34 wherein receiving a wafer which comprises a growth substrate and an epitaxial semiconductor layer grown on a first face of the growth substrate includes receiving a wafer in which the epitaxial semiconductor layer is Gallium Nitride, Silicon, or Silicon Carbide.

53. The method of claim 34 wherein receiving a wafer which comprises a growth substrate and an epitaxial semiconductor layer grown on a first face of the growth substrate includes receiving a wafer in which the epitaxial semiconductor layer comprises Silicon.

54. The method of claim 34 wherein receiving a wafer which comprises a growth substrate and an epitaxial semiconductor layer grown on a first face of the growth substrate includes receiving a wafer in which the epitaxial semiconductor layer comprises a material selected from the group consisting of GaN, InP, InGaAs, Si, SiC, and Ge.

55. The method of claim 36 wherein depositing a color conversion layer and adding a color filter layer comprise fabricating the color conversion layer and the color filter layer independently of the epitaxial semiconductor layer to create a color conversion module.

56. The method of claim 55; further comprising:

bonding the color conversion module to the back face of the epitaxial semiconductor layer.

57. The method of claim 56 wherein bonding the color conversion module to the back face of the epitaxial semiconductor layer comprises using metal bonding.

58. The method of claim 56 wherein bonding the color conversion module to the back face of the epitaxial semiconductor layer comprises using plasma fusion bonding.

59. The method of claim 56 wherein bonding the color conversion module to the back face of the epitaxial semiconductor layer comprises use of an adhesive.

60. The method of claim 56 wherein bonding the color conversion module to the back face of the epitaxial semiconductor layer comprises using anodic bonding.

61. A method of fabricating display structures; the method comprising:

receiving a wafer which comprises a growth substrate and an epitaxial semiconductor layer grown on a first face of the growth substrate;

patterning the epitaxial semiconductor layer of the wafer from a front face of the epitaxial semiconductor layer to form an interconnect layer comprising drive circuitry;

bonding the interconnect layer to a carrier substrate;

releasing the growth substrate from the epitaxial semiconductor layer to expose a back face of the epitaxial semiconductor layer, the back face opposed from the front face across a thickness of the epitaxial semiconductor layer; and

patterning one or more optical extraction elements on the back face of the epitaxial semiconductor layer, such that the interconnect layer, the epitaxial semiconductor layer, and the one or more optical extraction elements form a set of micro-light emitting diodes (micro-LEDs) controlled by the drive circuitry.

62. The method of claim 61 ; further comprising:

growing the epitaxial semiconductor layer on the first face of the growth substrate.

63. The method of claim 61 further comprising depositing an electrode on each of the one or more optical extraction elements.

64. The method of claim 61 wherein patterning one or more optical extraction elements comprises creating a prism.

65. The method of claim 61 wherein patterning one or more optical extraction elements comprises creating an optical grating.

66. The method of claim 61 wherein patterning one or more optical extraction elements comprises creating a photonic crystal.

67. The method of claim 61 wherein patterning one or more optical extraction elements comprises creating a lens.

68. The method of claim 67 wherein patterning one or more optical extraction elements comprises creating a shallow etched Fresnel lens.

69. The method of claim 61 wherein receiving a wafer which comprises a growth substrate and an epitaxial semiconductor layer grown on a first face of the growth substrate includes receiving a wafer in which the growth substrate is sapphire.

70. The method of claim 61 wherein receiving a wafer which comprises a growth substrate and an epitaxial semiconductor layer grown on a first face of the growth substrate includes receiving a wafer in which the epitaxial semiconductor layer is Gallium Nitride, Gallium Arsenide, Indium Phosphide, or comprises Silicon.

71. The method of claim 62 wherein growing the epitaxial semiconductor layer comprises allowing the semiconductor layer to grow to a thickness sufficient to accommodate a depth of the one or more optical extraction elements.

72. A method of fabricating display structures; the method comprising:

receiving a wafer which comprises a growth substrate and an epitaxial semiconductor layer grown on a first face of the growth substrate;

patterning the epitaxial semiconductor layer of the wafer from a front face of the epitaxial semiconductor layer to form an interconnect layer comprising drive circuitry;

bonding the interconnect layer to a carrier substrate;

polishing the growth substrate to create a residual growth substrate layer on a back face of the epitaxial semiconductor layer, the back face opposed from the front face across a thickness of the epitaxial semiconductor layer; and

patterning one or more optical extraction elements on the residual growth substrate layer, such that the interconnect layer, the epitaxial semiconductor layer, and the one or more optical extraction elements form a set of micro-light emitting diodes (micro-LEDs) controlled by the drive circuitry.

73. The method of claim 72; further comprising:

growing the epitaxial semiconductor layer on the first face of the growth substrate.

74. The method of claim 72 further comprising depositing an electrode on each of the one or more optical extraction elements.

75. The method of claim 72 further comprising depositing a mirror on each of the one or more optical extraction elements.

76. The method of claim 72 wherein patterning one or more optical extraction elements comprises creating a prism.

77. The method of claim 72 wherein patterning one or more optical extraction elements comprises creating an optical grating.

78. The method of claim 72 wherein patterning one or more optical extraction elements comprises creating a photonic crystal.

79. The method of claim 72 wherein patterning one or more optical extraction elements comprises creating a lens.

80. The method of claim 72 wherein patterning one or more optical extraction elements comprises creating a shallow etched Fresnel lens.

81. The method of claim 72 wherein patterning one or more optical extraction elements comprises creating a series of scattering elements.

82. The method of claim 72 wherein receiving a wafer which comprises a growth substrate and an epitaxial semiconductor layer grown on a first face of the growth substrate includes receiving a wafer in which the growth substrate is sapphire.

83. The method of claim 72 wherein receiving a wafer which comprises a growth substrate and an epitaxial semiconductor layer grown on a first face of the growth substrate includes receiving a wafer in which the epitaxial semiconductor layer is Gallium Nitride, Gallium Arsenide, Indium Phosphide, or comprises Silicon.

84. The method of claim 72 wherein polishing the growth substrate comprises allowing the residual growth substrate layer to remain at a thickness sufficient to accommodate a depth of the one or more optical extraction elements.

85. A display structure comprising:

a semiconductor device layer having a front face and a back face, the back face opposed from the front face across a thickness of the semiconductor device layer, and comprising a set of micro-light emitting diodes (micro-LEDs);

a carrier supporting the semiconductor device layer on the back face, the carrier having, for each respective micro-LED in the set of micro- LEDs, a respective aperture allowing light emitted by the respective micro-LED to exit the carrier; and

a bond electrically coupling each respective micro-LED in the set of micro-LEDs to the carrier.

86. The display structure of claim 85 wherein light emitted from a respective one of the micro- LEDs in the set of micro-LEDs is allowed to exit the carrier from the back face of the semiconductor device layer through the respective aperture and from the front face of the semiconductor device layer opposite the respective aperture.

87. The display structure of claim 85; further comprising:

for respective ones of the set of micro-LEDs, a respective reflective electrode to control a direction of light emitted from a respective micro-LED in the set of micro-LEDs.

88. The display structure of claim 87 wherein the respective reflective electrode is disposed on the back face of the semiconductor device layer proximal to the respective aperture to prevent light from exiting the respective aperture.

89. The display structure of claim 87 wherein the respective reflective electrode is disposed on the front face of the semiconductor device layer opposite the respective aperture to direct light through the respective aperture.

90. The display structure of claim 85 wherein the semiconductor device layer comprises Gallium Nitride or Silicon.

91. The display structure of claim 85 wherein the bond is a wire bond.

92. The display structure of claim 85 wherein the bond is a solder bump.