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1. WO2020133202 - REDUCE SYSTEM ACTIVE POWER BASED ON MEMORY USAGE PATTERNS

Publication Number WO/2020/133202
Publication Date 02.07.2020
International Application No. PCT/CN2018/124813
International Filing Date 28.12.2018
IPC
G11C 16/30 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
30Power supply circuits
G11C 5/14 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by group G11C11/63
14Power supply arrangements
CPC
G06F 1/10
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
04Generating or distributing clock signals or signals derived directly therefrom
10Distribution of clock signals ; , e.g. skew
G06F 1/3225
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
26Power supply means, e.g. regulation thereof
32Means for saving power
3203Power management, i.e. event-based initiation of power-saving mode
3206Monitoring of events, devices or parameters that trigger a change in power modality
3215Monitoring of peripheral devices
3225of memory devices
G06F 1/324
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
26Power supply means, e.g. regulation thereof
32Means for saving power
3203Power management, i.e. event-based initiation of power-saving mode
3234Power saving characterised by the action undertaken
324by lowering clock frequency
G06F 1/3275
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
26Power supply means, e.g. regulation thereof
32Means for saving power
3203Power management, i.e. event-based initiation of power-saving mode
3234Power saving characterised by the action undertaken
325Power saving in peripheral device
3275Power saving in memory, e.g. RAM, cache
G06F 11/1068
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1008in individual solid state devices
1068in sector programmable memories, e.g. flash disk
G06F 13/1668
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
1668Details of memory controller
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • DUAN, Xinghui
  • YUEN, Eric Kwok Fung
  • YU, Zhi Ping
  • WANG, Guanzhong
Agents
  • LEE AND LI - LEAVEN IPR AGENCY LTD.
Priority Data
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) REDUCE SYSTEM ACTIVE POWER BASED ON MEMORY USAGE PATTERNS
(FR) RÉDUCTION DE LA PUISSANCE ACTIVE D'UN SYSTÈME SUR LA BASE DE MOTIFS D'UTILISATION DE MÉMOIRE
Abstract
(EN)
A memory device comprises a memory array including memory cells, a communication interface to a host device, and a memory control unit operatively coupled to the memory array and the communication interface. The memory control unit is configured to store requests to access the memory in the queue, determine whether queued memory access requests are to sequential addresses of the memory array or to random addresses of the memory array, reduce an operating rate of one or more first components of the memory control unit when the queued memory access requests are to sequential addresses of the memory array, and reduce an operating rate of one or more second components of the memory control unit when the queued memory access requests are to random addresses of the memory array.
(FR)
L'invention concerne un dispositif de mémoire qui comprend un réseau de mémoire comprenant des cellules de mémoire, une interface de communication vers un dispositif hôte, et une unité de commande de mémoire couplée de manière fonctionnelle au réseau de mémoire et à l'interface de communication. L'unité de commande de mémoire est configurée pour stocker des demandes afin d'accéder à la mémoire dans la file d'attente, déterminer si des demandes d'accès à une mémoire en file d'attente correspondent à des adresses séquentielles du réseau de mémoire ou à des adresses aléatoires du réseau de mémoire, réduire une vitesse de fonctionnement d'un ou plusieurs premiers composants de l'unité de commande de mémoire lorsque les demandes d'accès à la mémoire en file d'attente correspondent à des adresses séquentielles du réseau de mémoire, et réduire une vitesse de fonctionnement d'un ou de plusieurs seconds composants de l'unité de commande de mémoire lorsque les demandes d'accès à la mémoire en file d'attente correspondent à des adresses aléatoires du réseau de mémoire.
Also published as
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