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Machine translation
1. (WO2007002445) MEMORY MICRO-TILING SPECULATIVE RETURNS
Note: Text based on automatic Optical Character Recognition processes. Please use the PDF version for legal matters

CLAIMS
What is claimed is:

1. A memory controller comprising:
assignment logic to receive a request to access a memory channel and to assign the request to access one of two or more subchannels within the channel; and
a transaction assembler to combine the request with one or more additional requests to access the two or more subchannels within the channel and to facilitate a speculative return of data from a subchannel for which a subchannel request is not available.

2. The memoiy controller of claim 1 wherein each of the subchannel requests include an independent address component and a shared address component.

3. The memory controller of claim 2 wherein the independent address component of a subchannel request is associated with a subchannel.

4. The memory controller of claim 3 wherein the transaction assembler facilitates the speculative return of data from a subchannel for which a request is not available, by selecting the independent address component to be associated with the subchannel for which a request is not be available.

5. The memory controller of claim 4 wherein the data speculatively read from the subchannel for which a request is not available, is returned to a requester.

6. The memory controller of claim 1 further comprising a reorder buffer to store the requests.

7. The memory controller of claim 6 wherein the reorder buffer includes a queue associated with each of the two or more subchannels.

8. The memory controller of claim 7 wherein each queue stores requests to be transferred to an associated subchannel.

9. A method comprising:
receiving a request at a memory controller to access a memory channel coupled to the memory controller;
assigning each of the requests to an associated independently addressable subchannel within the memory channel;
combining the request with one or more additional requests to access the two or more independently addressable subchannels within the channel; and
speculatively returning data from a subchannel for which a request is not available.

10. The method of claim 9 wherein the process of speculatively returning data from a subchannel for which a request is not available comprises selecting the independent address component to be associated with the subchannel for which a request is not be available.

11. The method of claim 9 further comprising storing the requests in a reorder buffer after assigning each of the requests to a subchannel.

12. The method of claim 9 further comprising forwarding the requests to the associated subchannels after assembling the requests.

13. The method of claim 10 further comprising returning the data speculatively returned from the subchannel for which a subchannel request is not be available to a requester.

14. A system comprising:
a memory device having one or more channels; and
a chipset, coupled to the memory device, having a memory controller to receive a request to access one of one or more memory channels, to assign the request to access one of two or more independently addressable subchannels within the channel, to combine the request with one or more additional requests to access the two or more independently addressable subchannels within the channel and to facilitate a speculative return of data from a subchannel for which a request is not available.

15. The system of claim 14 wherein comprises:
assignment logic to assign the request to access the subchannels; and

a transaction assembler to combine the requests and to facilitate the speculative return of data.

16. The system of claim 15 wherein the memory controller further comprises a reorder buffer to store the subchannel requests.

17. The system of claim 16 wherein the reorder buffer includes a queue associated with each of the two or more subchannels.

18. The system of claim 16 wherein the transaction assembler facilitates the speculative return of data from a subchannel for which a request is not available by selecting an independent address component to be associated with the subchannel for which a request is not available.

19. The system of claim 14 further comprising a requester coupled to the memory device and the memory controller, wherein the data speculatively read from the subchannel for which a request is not available is returned to the requester.
20. The system of claim 14 wherein the chipset comprises a second memory controller to receive a request to access one of one or more memory channels and to assign the request to access one of two or more independently addressable subchannels within the channel.