Processing

Please wait...

Settings

Settings

Goto Application

1. WO2021080829 - VOLTAGE PROFILE FOR REDUCTION OF READ DISTURB IN MEMORY CELLS

Publication Number WO/2021/080829
Publication Date 29.04.2021
International Application No. PCT/US2020/055563
International Filing Date 14.10.2020
IPC
G11C 13/00 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
13Digital stores characterised by the use of storage elements not covered by groups G11C11/, G11C23/, or G11C25/173
G11C 5/14 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by group G11C11/63
14Power supply arrangements
CPC
G11C 11/4085
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
408Address circuits
4085Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
G11C 11/4091
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write [R-W] circuits 
4091Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
G11C 13/0028
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
13Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
0002using resistive RAM [RRAM] elements
0021Auxiliary circuits
0023Address circuits or decoders
0028Word-line or row circuits
G11C 13/003
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
13Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
0002using resistive RAM [RRAM] elements
0021Auxiliary circuits
003Cell access
G11C 13/0033
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
13Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
0002using resistive RAM [RRAM] elements
0021Auxiliary circuits
0033Disturbance prevention or evaluation; Refreshing of disturbed memory data
G11C 13/0038
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
13Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
0002using resistive RAM [RRAM] elements
0021Auxiliary circuits
0038Power supply circuits
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • CUI, Mingdong
  • WANG, Hongmei
  • ISHAC, Michel Ibrahim
Agents
  • WARD, John P.
  • WANG, Lehua
Priority Data
16/660,59022.10.2019US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) VOLTAGE PROFILE FOR REDUCTION OF READ DISTURB IN MEMORY CELLS
(FR) PROFIL DE TENSION POUR LA RÉDUCTION DE PERTURBATION DE LECTURE DANS DES CELLULES DE MÉMOIRE
Abstract
(EN)
An integrated circuit memory device having: a memory cell; a current sensor connected to the memory cell; a voltage driver connected to the memory cell; and a bleed circuit connected to the voltage driver. During an operation to read the memory cell, the voltage driver drives a voltage applied on the memory cell. The bleed circuit is activated to reduce the voltage during a time period in which the current sensor operates to determine whether or not at least a predetermined level of current is presented in the memory cell.
(FR)
Un dispositif de mémoire à circuit intégré comprend : une cellule de mémoire ; un capteur de courant connecté à la cellule de mémoire ; un pilote de tension connecté à la cellule de mémoire ; et un circuit de purge connecté au pilote de tension. Pendant une opération de lecture de la cellule de mémoire, le pilote de tension commande une tension appliquée sur la cellule de mémoire. Le circuit de purge est activé pour réduire la tension pendant une période de temps dans laquelle le capteur de courant fonctionne afin de déterminer si au moins un niveau prédéterminé de courant est présent dans la cellule de mémoire.
Also published as
Latest bibliographic data on file with the International Bureau