Processing

Please wait...

Settings

Settings

Goto Application

1. WO2021080686 - SMALL LOOP DELAY CLOCK AND DATA RECOVERY BLOCK FOR HIGH-SPEED NEXT GENERATION C-PHY

Publication Number WO/2021/080686
Publication Date 29.04.2021
International Application No. PCT/US2020/047919
International Filing Date 26.08.2020
IPC
H04L 7/033 2006.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7Arrangements for synchronising receiver with transmitter
02Speed or phase control by the received code signals, the signals containing no special synchronisation information
033using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H04L 25/14 2006.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
25Baseband systems
02Details
14Channel dividing arrangements
G06F 13/40 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
40Bus structure
H04L 25/49 2006.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
25Baseband systems
38Synchronous or start-stop systems, e.g. for Baudot code
40Transmitting circuits; Receiving circuits
49using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels
CPC
G06F 13/4273
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
42Bus transfer protocol, e.g. handshake; Synchronisation
4265on a point to point bus
4273using a clocked protocol
G06F 13/4291
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
42Bus transfer protocol, e.g. handshake; Synchronisation
4282on a serial bus, e.g. I2C bus, SPI bus
4291using a clocked protocol
H04L 25/14
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
25Baseband systems
02Details
14Channel dividing arrangements ; in which a single bit stream is divided between several baseband channels and reassembled at the receiver
H04L 25/4917
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
25Baseband systems
38Synchronous or start-stop systems, e.g. for Baudot code
40Transmitting circuits; Receiving circuits
49using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; ; Baseband coding techniques specific to data transmission systems
4917using multilevel codes
H04L 7/0037
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7Arrangements for synchronising receiver with transmitter
0016correction of synchronization errors
0033Correction by delay
0037Delay of clock signal
H04L 7/0276
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7Arrangements for synchronising receiver with transmitter
02Speed or phase control by the received code signals, the signals containing no special synchronisation information
027extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
0276Self-sustaining, e.g. by tuned delay line and a feedback path to a logical gate
Applicants
  • QUALCOMM INCORPORATED [US]/[US]
Inventors
  • DUAN, Ying
  • WU, Jing
  • CHOU, Shih-Wei
Agents
  • SMYTH, Anthony
Priority Data
17/001,80125.08.2020US
62/925,91625.10.2019US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SMALL LOOP DELAY CLOCK AND DATA RECOVERY BLOCK FOR HIGH-SPEED NEXT GENERATION C-PHY
(FR) HORLOGE À RETARD DE PETITE BOUCLE ET BLOC DE RÉCUPÉRATION DE DONNÉES POUR UN C-PHY DE PROCHAINE GÉNÉRATION À GRANDE VITESSE
Abstract
(EN)
Methods, apparatus, and systems for communication over a multi-wire, multi-phase interface are disclosed. A clock recovery method includes generating a combination signal that includes transition pulses, each transition pulse being generated responsive to a transition in a difference signal representative of a difference in signaling state of a pair of wires in a three-wire bus. The combination signal is provided to a logic circuit that is configured to provide a clock signal as its output, where pulses in the combination signal cause the clock signal to be driven to a first state. The logic circuit receives a reset signal that is derived from the clock signal by delaying transitions to the first state while passing transitions from the first state without added delay. The clock signal is driven from the first state after passing a transition of the clock signal to the first state.
(FR)
La présente invention concerne des procédés, un appareil, et des systèmes pour une communication sur interface multiphasée à fils multiples. Un procédé de récupération d'horloge comprend la génération d'un signal de combinaison qui comprend des impulsions de transition, chaque impulsion de transition étant générée en réponse à une transition dans un signal de différence représentatif d'une différence dans un état de signalisation d'une paire de fils dans un bus à trois fils. Le signal de combinaison est fourni à un circuit logique qui est configuré pour fournir un signal d'horloge en sortie, des impulsions dans le signal de combinaison amenant le signal d'horloge à être entraîné vers un premier état. Le circuit logique reçoit un signal de réinitialisation qui est dérivé du signal d'horloge en retardant les transitions vers le premier état tout en faisant passer les transitions à partir du premier état sans retard ajouté. Le signal d'horloge est entraîné à partir du premier état après passage d'une transition du signal d'horloge vers le premier état.
Also published as
Latest bibliographic data on file with the International Bureau